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/gem5/src/arch/x86/insts/
H A Dmicroregop.hhdiff 4688:82d7cbf0e66d Tue Jul 17 18:33:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add in support for condition code flags.
Some microops can set the condition codes, and some of them can be predicated on them. Some of the codes aren't implemented because it was unclear from the AMD patent what they actually did. They are used with string instructions, but they use variables IP, DTF, and SSTF which don't appear to be documented.
H A Dmicroregop.ccdiff 4688:82d7cbf0e66d Tue Jul 17 18:33:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add in support for condition code flags.
Some microops can set the condition codes, and some of them can be predicated on them. Some of the codes aren't implemented because it was unclear from the AMD patent what they actually did. They are used with string instructions, but they use variables IP, DTF, and SSTF which don't appear to be documented.
/gem5/src/arch/x86/isa/microops/
H A Dregop.isadiff 4688:82d7cbf0e66d Tue Jul 17 18:33:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add in support for condition code flags.
Some microops can set the condition codes, and some of them can be predicated on them. Some of the codes aren't implemented because it was unclear from the AMD patent what they actually did. They are used with string instructions, but they use variables IP, DTF, and SSTF which don't appear to be documented.

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