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/gem5/src/dev/arm/
H A Dgic_v3_distributor.ccdiff 13812:3385c9418c82 Fri Mar 08 05:47:00 EST 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Writing ICENABLER for non-SPIs is RAZ/WI (or RES0)

For SGIs and PPIs:
* When ARE is 1 (only value supported in gem5) for the Security state of
an interrupt, the field for that interrupt is RES0 and an implementation
is permitted to make the field RAZ/WI in this case.

Change-Id: I6da2a89b1c848d458f42540e0113e7139b910abb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17630
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/arch/sparc/isa/
H A Dincludes.isadiff 3385:b28a1fd5a5c7 Mon Oct 23 02:36:00 EDT 2006 Gabe Black <gblack@eecs.umich.edu> Start making memory ops work with InitiateAcc and CompleteAcc, and some minor cleanups

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