Searched hist:3342 (Results 1 - 4 of 4) sorted by relevance

/gem5/src/cpu/
H A Dquiesce_event.ccdiff 3368:3342dd3f5248 Sun Oct 22 02:32:00 EDT 2006 Steve Reinhardt <stever@eecs.umich.edu> Add Quiesce trace flag to track CPU quiesce/wakeup events.
/gem5/src/mem/
H A Dtport.ccdiff 3342:19e716ad518e Fri Oct 20 13:01:00 EDT 2006 Ron Dreslinski <rdreslin@umich.edu> Use fixPacket function everywhere.
Fix fixPacket assert function.
Stop timing port from forwarding the request if a response was found in its queue on a read.

src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/python/m5/objects/MemTest.py:
Add parameter to configure what percentage of mem accesses are functional
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
Use fix Packet function
src/mem/packet.cc:
Fix an assert that was checking the wrong thing
src/mem/tport.cc:
Properly detect if we need to do the access to the functional device
H A Dpacket.ccdiff 3342:19e716ad518e Fri Oct 20 13:01:00 EDT 2006 Ron Dreslinski <rdreslin@umich.edu> Use fixPacket function everywhere.
Fix fixPacket assert function.
Stop timing port from forwarding the request if a response was found in its queue on a read.

src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/python/m5/objects/MemTest.py:
Add parameter to configure what percentage of mem accesses are functional
src/mem/cache/base_cache.cc:
src/mem/cache/cache_impl.hh:
Use fix Packet function
src/mem/packet.cc:
Fix an assert that was checking the wrong thing
src/mem/tport.cc:
Properly detect if we need to do the access to the functional device
/gem5/src/sim/
H A Dpseudo_inst.ccdiff 3368:3342dd3f5248 Sun Oct 22 02:32:00 EDT 2006 Steve Reinhardt <stever@eecs.umich.edu> Add Quiesce trace flag to track CPU quiesce/wakeup events.

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