Searched hist:31 (Results 501 - 525 of 1011) sorted by relevance
| /gem5/src/arch/mips/isa/formats/ | ||
| H A D | dsp.isa | diff 6383:31c067ae3331 Wed Jul 22 02:38:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Format the register index constants like the other ISAs. Also a few more style fixes. |
| /gem5/src/base/loader/ | ||
| H A D | ecoff_object.cc | diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info |
| /gem5/src/base/ | ||
| H A D | trace.cc | diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info |
| H A D | cprintf_formats.hh | diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info |
| /gem5/src/cpu/ | ||
| H A D | intr_control.hh | diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info |
| H A D | pc_event.hh | diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info |
| H A D | op_class.hh | diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info |
| /gem5/src/sim/ | ||
| H A D | drain.cc | diff 10998:cd22d66592bf Tue Aug 04 05:31:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> sim: Initialize Drainable::_drainState to the system's state It is sometimes desirable to be able to instantiate Drainable objects when the simulator isn't in the Running state. Currently, we always initialize Drainable objects to the Running state. However, this confuses many of the sanity checks in the base class since objects aren't expected to be in the Running state if the system is in the Draining or Drained state. Instead of always initializing the state variable in Drainable to DrainState::Running, initialize it to the state the DrainManager is in. Note: This means an object can be created in the Draining/Drained state without first calling drain(). |
| H A D | core.hh | diff 8737:770ccf3af571 Tue Jan 31 00:05:00 EST 2012 Koan-Sin Tan <koansin.tan@gmail.com> clang: Enable compiling gem5 using clang 2.9 and 3.0 This patch adds the necessary flags to the SConstruct and SConscript files for compiling using clang 2.9 and later (on Ubuntu et al and OSX XCode 4.2), and also cleans up a bunch of compiler warnings found by clang. Most of the warnings are related to hidden virtual functions, comparisons with unsigneds >= 0, and if-statements with empty bodies. A number of mismatches between struct and class are also fixed. clang 2.8 is not working as it has problems with class names that occur in multiple namespaces (e.g. Statistics in kernel_stats.hh). clang has a bug (http://llvm.org/bugs/show_bug.cgi?id=7247) which causes confusion between the container std::set and the function Packet::set, and this is currently addressed by not including the entire namespace std, but rather selecting e.g. "using std::vector" in the appropriate places. |
| /gem5/src/unittest/ | ||
| H A D | stattest.cc | diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info |
| /gem5/src/arch/x86/ | ||
| H A D | system.hh | diff 5627:31eac202dbd1 Sat Oct 11 02:43:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Create SimObjects in python and C++ to represent the ACPI system description tables. |
| /gem5/src/systemc/core/ | ||
| H A D | module.cc | 12863:ed8c2541cb30 Thu May 31 21:42:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Construct and manage a module name stack. Change-Id: I5f7f64d6c3d7e08ec6d2529f3c5d84fbfc2c421b Reviewed-on: https://gem5-review.googlesource.com/10850 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
| /gem5/src/arch/alpha/isa/ | ||
| H A D | unimp.isa | diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info |
| H A D | pal.isa | diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info |
| H A D | opcdec.isa | diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info |
| /gem5/src/arch/arm/isa/ | ||
| H A D | bitfields.isa | diff 10611:3bba9f2d0c7d Tue Dec 23 09:31:00 EST 2014 Andreas Sandberg <Andreas.Sandberg@ARM.com> arm: Raise an alignment fault if a PC has illegal alignment We currently don't handle unaligned PCs correctly. There is one check for unaligned PCs in the TLB when running in aarch64 mode, but this check does not cover cases where the CPU does not do a TLB lookup when decoding an instruction (e.g., a branch stays within the same cache line). Additionally, the Decoder class sometimes throws an assertion for unaligned PCs which breaks speculation. This changeset introduces a decoder fault bit field in the ExtMachInst structure. This field can be used to signal a decoder failure. If set, the decoder generates an internal gem5fault instruction instead of a normal instruction. This instruction in turns either panics (fault type PANIC), returns an PCAlignmentFault (fault type UNALIGNED, aarch64) or PrefetchAbort (fault type UNALIGNED, aarch32). The patch causes minor changes to the realview64 regressions, and a stats bump will follow. |
| /gem5/src/cpu/minor/ | ||
| H A D | fetch1.cc | diff 10950:d262e02c26b3 Fri Jul 31 12:04:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> cpu: Update debug message from Fetch1 isDrained() in Minor Fix a spurious %s and include the state of the Fetch1 stage in the debug printout. |
| /gem5/src/gpu-compute/ | ||
| H A D | wavefront.cc | diff 11643:42a1873be45c Fri Sep 16 00:31:00 EDT 2016 Alexandru Dutu <alexandru.dutu@amd.com> gpu-compute: Refactoring Wavefront::dynWaveId |
| /gem5/configs/common/ | ||
| H A D | SysPaths.py | diff 12233:53cf2e32cb59 Mon Oct 30 21:31:00 EDT 2017 Gabe Black <gabeblack@google.com> config: Rework the SysPaths functions into functors. These functions were already being treated as psuedo objects and had properties assigned to them setting what their paths were. That's a bit unusual and made it less obvious what the code was doing, but also forced the "system" function to know what all the possible path searching functions were so that they'd have their "path" property initialized properly in a central location. This change introduces a PathSearcFunc class which encapsulates the mechanisms of the old code and makes it implicitly extensible so that other path searching functions which might look in other directories can be added in other places. Change-Id: I7be28e51481a06ec83997677af99927709b18003 Reviewed-on: https://gem5-review.googlesource.com/5341 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/arch/alpha/linux/ | ||
| H A D | linux.hh | diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info |
| /gem5/src/arch/arm/ | ||
| H A D | decoder.hh | diff 10610:5fae03bd840a Tue Dec 23 09:31:00 EST 2014 Andreas Sandberg <Andreas.Sandberg@ARM.com> arm: Clean up and document decoder API This changeset adds more documentation to the ArmISA::Decoder class and restructures it slightly to make API groups more obvious. |
| /gem5/src/arch/arm/insts/ | ||
| H A D | pseudo.cc | 10611:3bba9f2d0c7d Tue Dec 23 09:31:00 EST 2014 Andreas Sandberg <Andreas.Sandberg@ARM.com> arm: Raise an alignment fault if a PC has illegal alignment We currently don't handle unaligned PCs correctly. There is one check for unaligned PCs in the TLB when running in aarch64 mode, but this check does not cover cases where the CPU does not do a TLB lookup when decoding an instruction (e.g., a branch stays within the same cache line). Additionally, the Decoder class sometimes throws an assertion for unaligned PCs which breaks speculation. This changeset introduces a decoder fault bit field in the ExtMachInst structure. This field can be used to signal a decoder failure. If set, the decoder generates an internal gem5fault instruction instead of a normal instruction. This instruction in turns either panics (fault type PANIC), returns an PCAlignmentFault (fault type UNALIGNED, aarch64) or PrefetchAbort (fault type UNALIGNED, aarch32). The patch causes minor changes to the realview64 regressions, and a stats bump will follow. |
| /gem5/src/arch/arm/isa/formats/ | ||
| H A D | formats.isa | diff 10611:3bba9f2d0c7d Tue Dec 23 09:31:00 EST 2014 Andreas Sandberg <Andreas.Sandberg@ARM.com> arm: Raise an alignment fault if a PC has illegal alignment We currently don't handle unaligned PCs correctly. There is one check for unaligned PCs in the TLB when running in aarch64 mode, but this check does not cover cases where the CPU does not do a TLB lookup when decoding an instruction (e.g., a branch stays within the same cache line). Additionally, the Decoder class sometimes throws an assertion for unaligned PCs which breaks speculation. This changeset introduces a decoder fault bit field in the ExtMachInst structure. This field can be used to signal a decoder failure. If set, the decoder generates an internal gem5fault instruction instead of a normal instruction. This instruction in turns either panics (fault type PANIC), returns an PCAlignmentFault (fault type UNALIGNED, aarch64) or PrefetchAbort (fault type UNALIGNED, aarch32). The patch causes minor changes to the realview64 regressions, and a stats bump will follow. |
| /gem5/src/arch/hsail/ | ||
| H A D | gen.py | diff 11643:42a1873be45c Fri Sep 16 00:31:00 EDT 2016 Alexandru Dutu <alexandru.dutu@amd.com> gpu-compute: Refactoring Wavefront::dynWaveId |
| /gem5/src/arch/sparc/linux/ | ||
| H A D | linux.hh | diff 2665:a124942bacb8 Wed May 31 19:26:00 EDT 2006 Ali Saidi <saidi@eecs.umich.edu> Updated Authors from bk prs info |
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