Searched hist:2973 (Results 1 - 3 of 3) sorted by relevance
/gem5/src/cpu/ | ||
H A D | exetrace.hh | diff 2973:56dea3a9d279 Fri Aug 11 20:21:00 EDT 2006 Gabe Black <gblack@eecs.umich.edu> Started adding a system to output data after every instruction. src/arch/alpha/regfile.hh: src/arch/mips/regfile/float_regfile.hh: src/arch/mips/regfile/int_regfile.hh: src/arch/mips/regfile/misc_regfile.hh: src/cpu/exetrace.hh: Added functions to start to support dumping register values once per cycle. src/cpu/exetrace.cc: Added some code to support printing the value of registers after each cycle. src/python/m5/main.py: Options to turn on output after every instruction. They are commented out. |
H A D | exetrace.cc | diff 2973:56dea3a9d279 Fri Aug 11 20:21:00 EDT 2006 Gabe Black <gblack@eecs.umich.edu> Started adding a system to output data after every instruction. src/arch/alpha/regfile.hh: src/arch/mips/regfile/float_regfile.hh: src/arch/mips/regfile/int_regfile.hh: src/arch/mips/regfile/misc_regfile.hh: src/cpu/exetrace.hh: Added functions to start to support dumping register values once per cycle. src/cpu/exetrace.cc: Added some code to support printing the value of registers after each cycle. src/python/m5/main.py: Options to turn on output after every instruction. They are commented out. |
/gem5/src/python/m5/ | ||
H A D | main.py | diff 2973:56dea3a9d279 Fri Aug 11 20:21:00 EDT 2006 Gabe Black <gblack@eecs.umich.edu> Started adding a system to output data after every instruction. src/arch/alpha/regfile.hh: src/arch/mips/regfile/float_regfile.hh: src/arch/mips/regfile/int_regfile.hh: src/arch/mips/regfile/misc_regfile.hh: src/cpu/exetrace.hh: Added functions to start to support dumping register values once per cycle. src/cpu/exetrace.cc: Added some code to support printing the value of registers after each cycle. src/python/m5/main.py: Options to turn on output after every instruction. They are commented out. |
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