Searched hist:2009 (Results 426 - 450 of 951) sorted by relevance
/gem5/src/mem/ruby/slicc_interface/ | ||
H A D | Message.hh | diff 6154:6bb54dcb940e Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Make ruby #includes use full paths to the files they're including. This basically means changing all #include statements and changing autogenerated code so that it generates the correct paths. Because slicc generates #includes, I had to hard code the include paths to mem/protocol. diff 6149:ff34514cbf37 Mon May 11 13:38:00 EDT 2009 Derek Hower <drh5@cs.wisc.edu> ruby: Renamed Ruby's EventQueue to RubyEventQueue 6145:15cca6ab723a Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import ruby and slicc from GEMS We eventually plan to replace the m5 cache hierarchy with the GEMS hierarchy, but for now we will make both live alongside eachother. |
H A D | AbstractCacheEntry.hh | diff 6285:ce086eca1ede Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import the latest ruby changes from gems. This was done with an automated process, so there could be things that were done in this tree in the past that didn't make it. One known regression is that atomic memory operations do not seem to work properly anymore. diff 6154:6bb54dcb940e Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Make ruby #includes use full paths to the files they're including. This basically means changing all #include statements and changing autogenerated code so that it generates the correct paths. Because slicc generates #includes, I had to hard code the include paths to mem/protocol. 6145:15cca6ab723a Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import ruby and slicc from GEMS We eventually plan to replace the m5 cache hierarchy with the GEMS hierarchy, but for now we will make both live alongside eachother. |
/gem5/src/dev/x86/ | ||
H A D | i8259.cc | diff 5898:541097c69e22 Wed Feb 25 13:16:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Add makeAtomicResponse to the read/write functions of x86 devices. diff 5830:1758d56964c9 Sun Feb 01 02:56:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Set up the console interrupt and add some DPRINTFs. diff 5827:ac2c268bf4f1 Sun Feb 01 02:33:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Rework interrupt pins to allow one to many connections. |
/gem5/src/mem/slicc/ast/ | ||
H A D | AST.py | 6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc. This is simply a translation of the C++ slicc into python with very minimal reorganization of the code. The output can be verified as nearly identical by doing a "diff -wBur". Slicc can easily be run manually by using util/slicc |
/gem5/src/arch/power/isa/ | ||
H A D | includes.isa | 6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA This adds support for the 32-bit, big endian Power ISA. This supports both integer and floating point instructions based on the Power ISA Book I v2.06. |
/gem5/src/arch/x86/isa/insts/x87/data_transfer_and_conversion/ | ||
H A D | load_or_store_floating_point.py | diff 6619:de112a8ac3d8 Thu Aug 20 03:42:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Fix the decoding for and fill out FST and FSTP. |
/gem5/src/arch/power/ | ||
H A D | pagetable.hh | 6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA This adds support for the 32-bit, big endian Power ISA. This supports both integer and floating point instructions based on the Power ISA Book I v2.06. |
H A D | pagetable.cc | 6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA This adds support for the 32-bit, big endian Power ISA. This supports both integer and floating point instructions based on the Power ISA Book I v2.06. |
H A D | locked_mem.hh | 6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA This adds support for the 32-bit, big endian Power ISA. This supports both integer and floating point instructions based on the Power ISA Book I v2.06. |
/gem5/src/base/ | ||
H A D | debug.hh | 5882:5a047c3f3795 Mon Feb 23 14:48:00 EST 2009 Nathan Binkert <nate@binkert.org> debug: Move debug_break into src/base |
H A D | debug.cc | 5882:5a047c3f3795 Mon Feb 23 14:48:00 EST 2009 Nathan Binkert <nate@binkert.org> debug: Move debug_break into src/base |
/gem5/src/mem/slicc/symbols/ | ||
H A D | Transition.py | 6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc. This is simply a translation of the C++ slicc into python with very minimal reorganization of the code. The output can be verified as nearly identical by doing a "diff -wBur". Slicc can easily be run manually by using util/slicc |
/gem5/src/arch/power/linux/ | ||
H A D | linux.hh | 6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA This adds support for the 32-bit, big endian Power ISA. This supports both integer and floating point instructions based on the Power ISA Book I v2.06. |
/gem5/src/mem/ruby/network/simple/ | ||
H A D | SimpleNetwork.hh | diff 6285:ce086eca1ede Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import the latest ruby changes from gems. This was done with an automated process, so there could be things that were done in this tree in the past that didn't make it. One known regression is that atomic memory operations do not seem to work properly anymore. diff 6284:a63d1dc4c820 Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: replace strings that were missed in original ruby import. diff 6154:6bb54dcb940e Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Make ruby #includes use full paths to the files they're including. This basically means changing all #include statements and changing autogenerated code so that it generates the correct paths. Because slicc generates #includes, I had to hard code the include paths to mem/protocol. 6145:15cca6ab723a Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import ruby and slicc from GEMS We eventually plan to replace the m5 cache hierarchy with the GEMS hierarchy, but for now we will make both live alongside eachother. |
H A D | SimpleNetwork.cc | diff 6795:394bc95d417b Wed Nov 18 19:34:00 EST 2009 Brad Beckmann <Brad.Beckmann@amd.com> ruby: removed the chip pointer from MessageBuffer The Chip object no longer exists and thus is removed from the MessageBuffer constructor. diff 6781:8da9d36fc14a Wed Nov 18 16:55:00 EST 2009 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Added default names to message buffers Added default names to message buffers created by the simple network. diff 6762:a22a47e60c21 Wed Nov 18 16:55:00 EST 2009 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Ruby destruction fix. diff 6372:f1a41ea3bbab Sat Jul 18 19:20:00 EDT 2009 Derek Hower <drh5@cs.wisc.edu> ruby: removed all refs to old RubyConfig diff 6294:b42cea5e1625 Wed Jul 08 00:01:00 EDT 2009 Derek Hower <drh5@cs.wisc.edu> removed stray debug print diff 6285:ce086eca1ede Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import the latest ruby changes from gems. This was done with an automated process, so there could be things that were done in this tree in the past that didn't make it. One known regression is that atomic memory operations do not seem to work properly anymore. diff 6284:a63d1dc4c820 Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: replace strings that were missed in original ruby import. diff 6154:6bb54dcb940e Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Make ruby #includes use full paths to the files they're including. This basically means changing all #include statements and changing autogenerated code so that it generates the correct paths. Because slicc generates #includes, I had to hard code the include paths to mem/protocol. 6145:15cca6ab723a Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import ruby and slicc from GEMS We eventually plan to replace the m5 cache hierarchy with the GEMS hierarchy, but for now we will make both live alongside eachother. |
/gem5/src/arch/mips/ | ||
H A D | pagetable.cc | diff 6378:4a2ff62c3b4f Tue Jul 21 04:08:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Many style fixes. White space, commented out code, some other minor fixes. |
H A D | dsp.cc | diff 6712:b95abe00dd9d Wed Nov 04 19:57:00 EST 2009 Nathan Binkert <nate@binkert.org> build: fix compile problems pointed out by gcc 4.4 |
H A D | locked_mem.hh | diff 6425:ed56e2cac9aa Fri Jul 31 09:34:00 EDT 2009 Korey Sewell <ksewell@umich.edu> mips: fix ll/sc pairs working incorrectly because of accidental clobber of LLFLAG diff 6383:31c067ae3331 Wed Jul 22 02:38:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Format the register index constants like the other ISAs. Also a few more style fixes. diff 6378:4a2ff62c3b4f Tue Jul 21 04:08:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> MIPS: Many style fixes. White space, commented out code, some other minor fixes. diff 6329:5d8b91875859 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Add a registers.hh file as an ISA switched header. This file is for register indices, Num* constants, and register types. copyRegs and copyMiscRegs were moved to utility.hh and utility.cc. |
/gem5/src/arch/x86/insts/ | ||
H A D | microldstop.cc | diff 5787:e3a6f53818fe Wed Jan 07 01:46:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> X86: Move the function that prints memory args into the inst base class. |
/gem5/src/sim/ | ||
H A D | simulate.hh | diff 6214:1ec0ec8933ae Sun May 17 17:34:00 EDT 2009 Nathan Binkert <nate@binkert.org> types: Move stuff for global types into src/base/types.hh |
/gem5/ | ||
H A D | .hgignore | diff 6792:64b815f299c0 Wed Nov 18 19:34:00 EST 2009 Brad Beckmann <Brad.Beckmann@amd.com> m5: Added the default m5out directory to the hg ignore list |
/gem5/src/arch/power/insts/ | ||
H A D | static_inst.cc | 6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA This adds support for the 32-bit, big endian Power ISA. This supports both integer and floating point instructions based on the Power ISA Book I v2.06. |
/gem5/src/arch/sparc/ | ||
H A D | SConscript | diff 6365:a3037fa327a0 Mon Jul 20 02:54:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> CPU: Separate out native trace into ISA (in)dependent code and SimObjects. diff 6335:a08470cb53e5 Thu Jul 09 23:28:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> SPARC: Fold the MiscRegFile all the way into the ISA object. diff 6329:5d8b91875859 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Add a registers.hh file as an ISA switched header. This file is for register indices, Num* constants, and register types. copyRegs and copyMiscRegs were moved to utility.hh and utility.cc. diff 6316:51f3026d4cbb Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Eliminate the ISA defined integer register file. diff 6315:c7295a4826d5 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Eliminate the ISA defined floating point register file. diff 6313:95f69a436c82 Thu Jul 09 02:02:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> Registers: Add an ISA object which replaces the MiscRegFile. This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU. diff 5938:fec76fcabf67 Wed Feb 25 13:21:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> SPARC: Add a traceflag for register windows. diff 5800:19c06c037040 Mon Jan 19 12:59:00 EST 2009 Nathan Binkert <nate@binkert.org> tracing: Add help strings for some of the trace flags diff 5793:321f79ddb500 Tue Jan 13 17:17:00 EST 2009 Nathan Binkert <nate@binkert.org> SCons: centralize the Dir() workaround for newer versions of scons. Scons bug id: 2006 M5 Bug id: 308 |
/gem5/src/mem/ruby/network/ | ||
H A D | Network.cc | diff 6700:deb871e1fc27 Wed Oct 28 14:56:00 EDT 2009 Nathan Binkert <nate@binkert.org> license: Fix license on network model code This mostly was a matter of changing the license owner to Princeton which is as it should have been. The code was originally licensed under the GPL but was relicensed as BSD by Li-Shiuan Peh on July 27, 2009. This relicensing was in an explicit e-mail to Nathan Binkert, Brad Beckmann, Mark Hill, David Wood, and Steve Reinhardt. diff 6700:deb871e1fc27 Wed Oct 28 14:56:00 EDT 2009 Nathan Binkert <nate@binkert.org> license: Fix license on network model code This mostly was a matter of changing the license owner to Princeton which is as it should have been. The code was originally licensed under the GPL but was relicensed as BSD by Li-Shiuan Peh on July 27, 2009. This relicensing was in an explicit e-mail to Nathan Binkert, Brad Beckmann, Mark Hill, David Wood, and Steve Reinhardt. diff 6493:1fa51760a963 Fri Aug 07 16:59:00 EDT 2009 Tushar Krishna <Tushar.Krishna@amd.com> bug fix for data_msg_size in network/Network.cc 6285:ce086eca1ede Mon Jul 06 18:49:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: Import the latest ruby changes from gems. This was done with an automated process, so there could be things that were done in this tree in the past that didn't make it. One known regression is that atomic memory operations do not seem to work properly anymore. |
/gem5/tests/ | ||
H A D | SConscript | diff 6293:a37f8971b271 Tue Jul 07 01:45:00 EDT 2009 Steve Reinhardt <steve.reinhardt@amd.com> Add ability to skip tests by adding 'skip' file to test dir, and skip simple-timing-mp-ruby test for now (until we fix ruby atomics). diff 6194:2078ba7cefe4 Tue May 12 15:01:00 EDT 2009 Korey Sewell <ksewell@umich.edu> inorder-regress: add hello world diff 6168:ba6fe02228db Mon May 11 13:38:00 EDT 2009 Nathan Binkert <nate@binkert.org> ruby: add RUBY sticky option that must be set to add ruby to the build Default is false diff 6166:6fad2d8345b7 Mon May 11 13:38:00 EDT 2009 Steve Reinhardt <steve.reinhardt@amd.com> ruby: Set up Ruby regression tests. diff 6112:21f6eaab12df Tue Apr 21 11:37:00 EDT 2009 Steve Reinhardt <steve.reinhardt@amd.com> Set up m5threads tests on classic (non-ruby) memory system. Just one test (40.m5threads-test-atomic) is set up for now. These tests require that the m5threads SPARC binaries are present in /dist or in test-progs. diff 6025:044903442dcb Thu Apr 09 01:22:00 EDT 2009 Nathan Binkert <nate@binkert.org> alpha: get rid of all turbolaser remnants diff 6011:27836c06d13d Wed Mar 11 13:54:00 EDT 2009 Steve Reinhardt <steve.reinhardt@amd.com> tests: use env.Execute instead of Execute to pick up env vars. diff 6008:fb50ea61a226 Sat Mar 07 20:24:00 EST 2009 Steve Reinhardt <steve.reinhardt@amd.com> Minor tweak to regression exit status message. diff 6007:e0344c15e73b Sat Mar 07 19:58:00 EST 2009 Steve Reinhardt <steve.reinhardt@amd.com> Fix up regression execution to better handle tests that end abnormally. E.g., mark aborts due to assertion failures as failed tests, but those that get killed by the user as needing to be rerun, etc. |
Completed in 141 milliseconds