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H A D | gic_v3_cpu_interface.cc | diff 14248:36750190a8ed Mon Sep 02 06:26:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: State update when setting MISCREG_ICC_IGRPENx register This is because by enabling ainterrupt group at the cpu interface, we need to check if a previously pending interrupt needs to be forwarded to the PE. We are doing the same when globally enabling irqs in the distributor (GICD_CTLR). Change-Id: I80aeb87b2a58a108de899006d5a2f12eadbe6c2e Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20629 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com> |
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