Searched hist:13067 (Results 1 - 4 of 4) sorted by relevance
| /gem5/src/arch/arm/ | ||
| H A D | miscregs_types.hh | diff 13117:59959c5d7438 Tue Sep 25 12:37:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Implement AArch64 ID regs as bitunions This patch is implementing the following AArch64 ID registers as bitunions, so that it is easier to query for feature availability: - ID_AA64DFR0_EL1 - ID_AA64ISAR0_EL1 - ID_AA64ISAR1_EL1 - ID_AA64MMFR1_EL1 - ID_AA64MMFR2_EL1 - ID_AA64PFR0_EL1 They are updated to the latest Armv8.5 arch release version. RES0 only ID registers like ID_AA64AFR1_EL1 haven't been added. Change-Id: Ied037abe3757421bcfc2834d397a8cf9a2b9f0a7 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/13067 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| /gem5/src/systemc/core/ | ||
| H A D | kernel.cc | diff 13067:3d6ef32002ef Thu Aug 16 23:59:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Rework the init phase for the new way delta notes are handled. The initialization phase had been done in a somewhat adhoc way, partially because delta notifications were being handled as top level gem5 events which were ordered based on their priorities. This change makes the initialization phase happen more explicitly, and more in the order in the spec. Change-Id: I91d56b63fefcb81c845c52c97826a976a7559fad Reviewed-on: https://gem5-review.googlesource.com/12217 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
| H A D | scheduler.hh | diff 13067:3d6ef32002ef Thu Aug 16 23:59:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Rework the init phase for the new way delta notes are handled. The initialization phase had been done in a somewhat adhoc way, partially because delta notifications were being handled as top level gem5 events which were ordered based on their priorities. This change makes the initialization phase happen more explicitly, and more in the order in the spec. Change-Id: I91d56b63fefcb81c845c52c97826a976a7559fad Reviewed-on: https://gem5-review.googlesource.com/12217 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
| H A D | scheduler.cc | diff 13067:3d6ef32002ef Thu Aug 16 23:59:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Rework the init phase for the new way delta notes are handled. The initialization phase had been done in a somewhat adhoc way, partially because delta notifications were being handled as top level gem5 events which were ordered based on their priorities. This change makes the initialization phase happen more explicitly, and more in the order in the spec. Change-Id: I91d56b63fefcb81c845c52c97826a976a7559fad Reviewed-on: https://gem5-review.googlesource.com/12217 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
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