Searched hist:12816 (Results 1 - 5 of 5) sorted by relevance
| /gem5/src/systemc/tests/systemc/communication/ports/test05/ | ||
| H A D | expected_returncode | 13239:0fe49a9e1754 Sat Sep 15 19:20:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Add an error check whether an interface is alread bound to a port. Change-Id: I06e3484176c0c06daa28f7be0ed8437b3b15ddb2 Reviewed-on: https://gem5-review.googlesource.com/c/12816 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
| /gem5/src/systemc/core/ | ||
| H A D | port.hh | diff 13239:0fe49a9e1754 Sat Sep 15 19:20:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Add an error check whether an interface is alread bound to a port. Change-Id: I06e3484176c0c06daa28f7be0ed8437b3b15ddb2 Reviewed-on: https://gem5-review.googlesource.com/c/12816 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
| /gem5/src/arch/arm/ | ||
| H A D | miscregs.cc | diff 12816:9e9bd9e6e206 Thu May 17 12:19:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Introduce ARMv8.1 Virtual Timer System Registers Adding CNTHV_CTL_EL2, CNTHV_CVAL_EL2, CNTHV_TVAL_EL2 System Registers into the decode tree. They are currently implemented as a generic timer and produces a warning if accessed. Change-Id: I1a23035d67f95eeac49d890283e9a0d58426d504 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11592 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | miscregs.hh | diff 12816:9e9bd9e6e206 Thu May 17 12:19:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Introduce ARMv8.1 Virtual Timer System Registers Adding CNTHV_CTL_EL2, CNTHV_CVAL_EL2, CNTHV_TVAL_EL2 System Registers into the decode tree. They are currently implemented as a generic timer and produces a warning if accessed. Change-Id: I1a23035d67f95eeac49d890283e9a0d58426d504 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11592 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
| H A D | isa.cc | diff 12816:9e9bd9e6e206 Thu May 17 12:19:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Introduce ARMv8.1 Virtual Timer System Registers Adding CNTHV_CTL_EL2, CNTHV_CVAL_EL2, CNTHV_TVAL_EL2 System Registers into the decode tree. They are currently implemented as a generic timer and produces a warning if accessed. Change-Id: I1a23035d67f95eeac49d890283e9a0d58426d504 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/11592 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> |
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