Searched hist:12320 (Results 1 - 7 of 7) sorted by relevance
| /gem5/src/arch/riscv/insts/ | ||
| H A D | standard.hh | 12320:d846aaaa33b1 Tue Nov 07 14:15:00 EST 2017 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Move standard ops out of ISA This patch removes static portions of the standard instruction types from the generated ISA code and puts them into arch/riscv/insts. Some dynamically-generated content is left behind for each individual instruction's implementation. Also, BranchOp is removed due to its similarity with ImmOp and ImmOp and UImmOp are joined into a single templated class, ImmOp<T>. Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a Reviewed-on: https://gem5-review.googlesource.com/6022 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu> |
| H A D | bitfields.hh | 12320:d846aaaa33b1 Tue Nov 07 14:15:00 EST 2017 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Move standard ops out of ISA This patch removes static portions of the standard instruction types from the generated ISA code and puts them into arch/riscv/insts. Some dynamically-generated content is left behind for each individual instruction's implementation. Also, BranchOp is removed due to its similarity with ImmOp and ImmOp and UImmOp are joined into a single templated class, ImmOp<T>. Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a Reviewed-on: https://gem5-review.googlesource.com/6022 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu> |
| H A D | standard.cc | 12320:d846aaaa33b1 Tue Nov 07 14:15:00 EST 2017 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Move standard ops out of ISA This patch removes static portions of the standard instruction types from the generated ISA code and puts them into arch/riscv/insts. Some dynamically-generated content is left behind for each individual instruction's implementation. Also, BranchOp is removed due to its similarity with ImmOp and ImmOp and UImmOp are joined into a single templated class, ImmOp<T>. Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a Reviewed-on: https://gem5-review.googlesource.com/6022 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu> |
| H A D | SConscript | diff 12320:d846aaaa33b1 Tue Nov 07 14:15:00 EST 2017 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Move standard ops out of ISA This patch removes static portions of the standard instruction types from the generated ISA code and puts them into arch/riscv/insts. Some dynamically-generated content is left behind for each individual instruction's implementation. Also, BranchOp is removed due to its similarity with ImmOp and ImmOp and UImmOp are joined into a single templated class, ImmOp<T>. Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a Reviewed-on: https://gem5-review.googlesource.com/6022 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu> |
| /gem5/src/arch/riscv/isa/formats/ | ||
| H A D | compressed.isa | diff 12320:d846aaaa33b1 Tue Nov 07 14:15:00 EST 2017 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Move standard ops out of ISA This patch removes static portions of the standard instruction types from the generated ISA code and puts them into arch/riscv/insts. Some dynamically-generated content is left behind for each individual instruction's implementation. Also, BranchOp is removed due to its similarity with ImmOp and ImmOp and UImmOp are joined into a single templated class, ImmOp<T>. Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a Reviewed-on: https://gem5-review.googlesource.com/6022 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu> |
| H A D | standard.isa | diff 12320:d846aaaa33b1 Tue Nov 07 14:15:00 EST 2017 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Move standard ops out of ISA This patch removes static portions of the standard instruction types from the generated ISA code and puts them into arch/riscv/insts. Some dynamically-generated content is left behind for each individual instruction's implementation. Also, BranchOp is removed due to its similarity with ImmOp and ImmOp and UImmOp are joined into a single templated class, ImmOp<T>. Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a Reviewed-on: https://gem5-review.googlesource.com/6022 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu> |
| /gem5/src/arch/riscv/isa/ | ||
| H A D | includes.isa | diff 12320:d846aaaa33b1 Tue Nov 07 14:15:00 EST 2017 Alec Roelke <ar4jc@virginia.edu> arch-riscv: Move standard ops out of ISA This patch removes static portions of the standard instruction types from the generated ISA code and puts them into arch/riscv/insts. Some dynamically-generated content is left behind for each individual instruction's implementation. Also, BranchOp is removed due to its similarity with ImmOp and ImmOp and UImmOp are joined into a single templated class, ImmOp<T>. Change-Id: I1bf47c8b8a92a5be74a50909fcc51d8551185a2a Reviewed-on: https://gem5-review.googlesource.com/6022 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Alec Roelke <ar4jc@virginia.edu> |
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