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/gem5/src/systemc/core/
H A Dsc_time.ccdiff 13124:538eff58fb30 Tue Aug 28 01:55:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Implement support for the default time unit.

This is deprecated, but still used in the tests.

Change-Id: I454540e419c53624a37f3d1271cb240415b816b6
Reviewed-on: https://gem5-review.googlesource.com/c/12276
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/cpu/minor/
H A Dcpu.ccdiff 12276:22c220be30c5 Thu Mar 16 20:02:00 EDT 2017 Anouk Van Laer <anouk.vanlaer@arm.com> pwr: Adds logic to enter power gating for the cpu model

If the CPU has been clock gated for a sufficient amount of time
(configurable via pwrGatingLatency), the CPU will go into the OFF
power state. This does not model hardware, just behaviour.

Change-Id: Ib3681d1ffa6ad25eba60f47b4020325f63472d43
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3969
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/cpu/
H A DBaseCPU.pydiff 12276:22c220be30c5 Thu Mar 16 20:02:00 EDT 2017 Anouk Van Laer <anouk.vanlaer@arm.com> pwr: Adds logic to enter power gating for the cpu model

If the CPU has been clock gated for a sufficient amount of time
(configurable via pwrGatingLatency), the CPU will go into the OFF
power state. This does not model hardware, just behaviour.

Change-Id: Ib3681d1ffa6ad25eba60f47b4020325f63472d43
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3969
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
H A Dbase.ccdiff 12276:22c220be30c5 Thu Mar 16 20:02:00 EDT 2017 Anouk Van Laer <anouk.vanlaer@arm.com> pwr: Adds logic to enter power gating for the cpu model

If the CPU has been clock gated for a sufficient amount of time
(configurable via pwrGatingLatency), the CPU will go into the OFF
power state. This does not model hardware, just behaviour.

Change-Id: Ib3681d1ffa6ad25eba60f47b4020325f63472d43
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3969
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
H A Dbase.hhdiff 12276:22c220be30c5 Thu Mar 16 20:02:00 EDT 2017 Anouk Van Laer <anouk.vanlaer@arm.com> pwr: Adds logic to enter power gating for the cpu model

If the CPU has been clock gated for a sufficient amount of time
(configurable via pwrGatingLatency), the CPU will go into the OFF
power state. This does not model hardware, just behaviour.

Change-Id: Ib3681d1ffa6ad25eba60f47b4020325f63472d43
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3969
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/cpu/simple/
H A Dtiming.ccdiff 12276:22c220be30c5 Thu Mar 16 20:02:00 EDT 2017 Anouk Van Laer <anouk.vanlaer@arm.com> pwr: Adds logic to enter power gating for the cpu model

If the CPU has been clock gated for a sufficient amount of time
(configurable via pwrGatingLatency), the CPU will go into the OFF
power state. This does not model hardware, just behaviour.

Change-Id: Ib3681d1ffa6ad25eba60f47b4020325f63472d43
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3969
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
H A Datomic.ccdiff 12276:22c220be30c5 Thu Mar 16 20:02:00 EDT 2017 Anouk Van Laer <anouk.vanlaer@arm.com> pwr: Adds logic to enter power gating for the cpu model

If the CPU has been clock gated for a sufficient amount of time
(configurable via pwrGatingLatency), the CPU will go into the OFF
power state. This does not model hardware, just behaviour.

Change-Id: Ib3681d1ffa6ad25eba60f47b4020325f63472d43
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3969
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/cpu/o3/
H A Dcpu.ccdiff 12276:22c220be30c5 Thu Mar 16 20:02:00 EDT 2017 Anouk Van Laer <anouk.vanlaer@arm.com> pwr: Adds logic to enter power gating for the cpu model

If the CPU has been clock gated for a sufficient amount of time
(configurable via pwrGatingLatency), the CPU will go into the OFF
power state. This does not model hardware, just behaviour.

Change-Id: Ib3681d1ffa6ad25eba60f47b4020325f63472d43
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/3969
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

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