Searched hist:11355 (Results 1 - 4 of 4) sorted by relevance

/gem5/src/systemc/ext/channel/
H A Dsc_signal.hhdiff 12945:365bae01b46d Mon Jun 18 22:07:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Add m_cur_val and m_new_val to sc_signal.

These members are referred to in one of the tests.

Change-Id: Iab0110a0e3acf627986664069622704f17b703a1
Reviewed-on: https://gem5-review.googlesource.com/11355
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/arch/arm/isa/insts/
H A Ddata.isadiff 11355:46c7b3e35720 Mon Feb 29 20:13:00 EST 2016 Mitch Hayenga <mitch.hayenga@arm.com> arm: Squash after returning from exceptions in v7

Properly done for the ERET instruction in v8, but not for v7.
Many control register changes are only visible after explicit
instruction synchronization barriers or exception entry/exit.
This means mode changing instructions should squash any
younger in-flight speculative instructions.
H A Dmacromem.isadiff 11355:46c7b3e35720 Mon Feb 29 20:13:00 EST 2016 Mitch Hayenga <mitch.hayenga@arm.com> arm: Squash after returning from exceptions in v7

Properly done for the ERET instruction in v8, but not for v7.
Many control register changes are only visible after explicit
instruction synchronization barriers or exception entry/exit.
This means mode changing instructions should squash any
younger in-flight speculative instructions.
H A Dmisc.isadiff 11355:46c7b3e35720 Mon Feb 29 20:13:00 EST 2016 Mitch Hayenga <mitch.hayenga@arm.com> arm: Squash after returning from exceptions in v7

Properly done for the ERET instruction in v8, but not for v7.
Many control register changes are only visible after explicit
instruction synchronization barriers or exception entry/exit.
This means mode changing instructions should squash any
younger in-flight speculative instructions.

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