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| /gem5/src/arch/x86/insts/ | ||
| H A D | microldstop.cc | diff 11329:82bb3ee706b3 Sat Feb 06 20:21:00 EST 2016 Alexandru Dutu <alexandru.dutu@amd.com> x86: revamp cmpxchg8b/cmpxchg16b implementation The previous implementation did a pair of nested RMW operations, which isn't compatible with the way that locked RMW operations are implemented in the cache models. It was convenient though in that it didn't require any new micro-ops, and supported cmpxchg16b using 64-bit memory ops. It also worked in AtomicSimpleCPU where atomicity was guaranteed by the core and not by the memory system. It did not work with timing CPU models though. This new implementation defines new 'split' load and store micro-ops which allow a single memory operation to use a pair of registers as the source or destination, then uses a single ldsplit/stsplit RMW pair to implement cmpxchg. This patch requires support for 128-bit memory accesses in the ISA (added via a separate patch) to support cmpxchg16b. |
| H A D | microldstop.hh | diff 11329:82bb3ee706b3 Sat Feb 06 20:21:00 EST 2016 Alexandru Dutu <alexandru.dutu@amd.com> x86: revamp cmpxchg8b/cmpxchg16b implementation The previous implementation did a pair of nested RMW operations, which isn't compatible with the way that locked RMW operations are implemented in the cache models. It was convenient though in that it didn't require any new micro-ops, and supported cmpxchg16b using 64-bit memory ops. It also worked in AtomicSimpleCPU where atomicity was guaranteed by the core and not by the memory system. It did not work with timing CPU models though. This new implementation defines new 'split' load and store micro-ops which allow a single memory operation to use a pair of registers as the source or destination, then uses a single ldsplit/stsplit RMW pair to implement cmpxchg. This patch requires support for 128-bit memory accesses in the ISA (added via a separate patch) to support cmpxchg16b. |
| /gem5/src/arch/x86/isa/insts/general_purpose/ | ||
| H A D | semaphores.py | diff 11329:82bb3ee706b3 Sat Feb 06 20:21:00 EST 2016 Alexandru Dutu <alexandru.dutu@amd.com> x86: revamp cmpxchg8b/cmpxchg16b implementation The previous implementation did a pair of nested RMW operations, which isn't compatible with the way that locked RMW operations are implemented in the cache models. It was convenient though in that it didn't require any new micro-ops, and supported cmpxchg16b using 64-bit memory ops. It also worked in AtomicSimpleCPU where atomicity was guaranteed by the core and not by the memory system. It did not work with timing CPU models though. This new implementation defines new 'split' load and store micro-ops which allow a single memory operation to use a pair of registers as the source or destination, then uses a single ldsplit/stsplit RMW pair to implement cmpxchg. This patch requires support for 128-bit memory accesses in the ISA (added via a separate patch) to support cmpxchg16b. |
| /gem5/src/arch/x86/isa/ | ||
| H A D | operands.isa | diff 11329:82bb3ee706b3 Sat Feb 06 20:21:00 EST 2016 Alexandru Dutu <alexandru.dutu@amd.com> x86: revamp cmpxchg8b/cmpxchg16b implementation The previous implementation did a pair of nested RMW operations, which isn't compatible with the way that locked RMW operations are implemented in the cache models. It was convenient though in that it didn't require any new micro-ops, and supported cmpxchg16b using 64-bit memory ops. It also worked in AtomicSimpleCPU where atomicity was guaranteed by the core and not by the memory system. It did not work with timing CPU models though. This new implementation defines new 'split' load and store micro-ops which allow a single memory operation to use a pair of registers as the source or destination, then uses a single ldsplit/stsplit RMW pair to implement cmpxchg. This patch requires support for 128-bit memory accesses in the ISA (added via a separate patch) to support cmpxchg16b. |
| /gem5/src/arch/x86/isa/microops/ | ||
| H A D | ldstop.isa | diff 11329:82bb3ee706b3 Sat Feb 06 20:21:00 EST 2016 Alexandru Dutu <alexandru.dutu@amd.com> x86: revamp cmpxchg8b/cmpxchg16b implementation The previous implementation did a pair of nested RMW operations, which isn't compatible with the way that locked RMW operations are implemented in the cache models. It was convenient though in that it didn't require any new micro-ops, and supported cmpxchg16b using 64-bit memory ops. It also worked in AtomicSimpleCPU where atomicity was guaranteed by the core and not by the memory system. It did not work with timing CPU models though. This new implementation defines new 'split' load and store micro-ops which allow a single memory operation to use a pair of registers as the source or destination, then uses a single ldsplit/stsplit RMW pair to implement cmpxchg. This patch requires support for 128-bit memory accesses in the ISA (added via a separate patch) to support cmpxchg16b. |
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