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| /gem5/src/mem/cache/ | ||
| H A D | base.hh | diff 10344:fa9ef374075f Wed Sep 03 07:42:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Fix a bug in the cache port flow control This patch fixes a bug in the cache port where the retry flag was reset too early, allowing new requests to arrive before the retry was actually sent, but with the event already scheduled. This caused a deadlock in the interactions with the O3 LSQ. The patche fixes the underlying issue by shifting the resetting of the flag to be done by the event that also calls sendRetry(). The patch also tidies up the flow control in recvTimingReq and ensures that we also check if we already have a retry outstanding. |
| H A D | base.cc | diff 10344:fa9ef374075f Wed Sep 03 07:42:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> mem: Fix a bug in the cache port flow control This patch fixes a bug in the cache port where the retry flag was reset too early, allowing new requests to arrive before the retry was actually sent, but with the event already scheduled. This caused a deadlock in the interactions with the O3 LSQ. The patche fixes the underlying issue by shifting the resetting of the flag to be done by the event that also calls sendRetry(). The patch also tidies up the flow control in recvTimingReq and ensures that we also check if we already have a retry outstanding. |
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