Searched hist:10188 (Results 1 - 3 of 3) sorted by relevance
| /gem5/src/arch/arm/isa/insts/ | ||
| H A D | misc.isa | diff 10188:c09802451018 Fri May 09 18:58:00 EDT 2014 Geoffrey Blake <geoffrey.blake@arm.com> arm: Panics in miscreg read functions can be tripped by O3 model Unimplemented miscregs for the generic timer were guarded by panics in arm/isa.cc which can be tripped by the O3 model if it speculatively executes a wrong path containing a mrs instruction with a bad miscreg index. These registers were flagged as implemented and accessible. This patch changes the miscreg info bit vector to flag them as unimplemented and inaccessible. In this case, and UndefinedInst fault will be generated if the register access is not trapped by a hypervisor. |
| /gem5/src/arch/arm/ | ||
| H A D | miscregs.cc | diff 10188:c09802451018 Fri May 09 18:58:00 EDT 2014 Geoffrey Blake <geoffrey.blake@arm.com> arm: Panics in miscreg read functions can be tripped by O3 model Unimplemented miscregs for the generic timer were guarded by panics in arm/isa.cc which can be tripped by the O3 model if it speculatively executes a wrong path containing a mrs instruction with a bad miscreg index. These registers were flagged as implemented and accessible. This patch changes the miscreg info bit vector to flag them as unimplemented and inaccessible. In this case, and UndefinedInst fault will be generated if the register access is not trapped by a hypervisor. |
| H A D | isa.cc | diff 10188:c09802451018 Fri May 09 18:58:00 EDT 2014 Geoffrey Blake <geoffrey.blake@arm.com> arm: Panics in miscreg read functions can be tripped by O3 model Unimplemented miscregs for the generic timer were guarded by panics in arm/isa.cc which can be tripped by the O3 model if it speculatively executes a wrong path containing a mrs instruction with a bad miscreg index. These registers were flagged as implemented and accessible. This patch changes the miscreg info bit vector to flag them as unimplemented and inaccessible. In this case, and UndefinedInst fault will be generated if the register access is not trapped by a hypervisor. |
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