| /gem5/src/arch/generic/ |
| H A D | BaseTLB.py | 40 master = MasterPort("Port closer to memory side") variable in class:BaseTLB
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| /gem5/src/mem/qos/ |
| H A D | policy.hh | 115 Policy::pair(M master, T value) argument
[all...] |
| H A D | policy_fixed_prio.cc | 62 FixedPriorityPolicy::initMasterName(std::string master, uint8_t priority) argument
69 FixedPriorityPolicy::initMasterObj(const SimObject* master, uint8_t priority) argument
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| H A D | mem_ctrl.cc | 323 const std::string master = _system->getMasterName(i); local
[all...] |
| H A D | policy_pf.cc | 58 PropFairPolicy::initMaster(const Master master, const double score) argument
73 PropFairPolicy::initMasterName(const std::string master, const double score) argument
79 PropFairPolicy::initMasterObj(const SimObject* master, const double score) argument
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| /gem5/src/mem/ruby/network/ |
| H A D | MessageBuffer.py | 45 master = MasterPort("Master port to MessageBuffer receiver") variable in class:MessageBuffer
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| H A D | Network.py | 56 master = VectorMasterPort("CPU master port") variable in class:RubyNetwork
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| /gem5/src/mem/ |
| H A D | Bridge.py | 49 master = MasterPort('Master port') variable in class:Bridge
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| H A D | AddrMapper.py | 53 master = MasterPort("Master port") variable in class:AddrMapper
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| H A D | MemChecker.py | 51 master = MasterPort("Master port") variable in class:MemCheckerMonitor
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| H A D | SerialLink.py | 54 master = MasterPort('Master port') variable in class:SerialLink
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| H A D | MemDelay.py | 46 master = MasterPort("Master port") variable in class:MemDelay
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| H A D | CommMonitor.py | 53 master = MasterPort("Master port") variable in class:CommMonitor
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| H A D | XBar.py | 55 master = VectorMasterPort("Vector port for connecting slaves") variable in class:BaseXBar
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| H A D | noncoherent_xbar.cc | 265 auto master = masterPorts[master_port_id]; local
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| /gem5/system/alpha/console/ |
| H A D | dbmentry.S | 97 master: label
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| /gem5/src/sim/probe/ |
| H A D | mem.hh | 60 MasterID master; member in struct:ProbePoints::PacketInfo
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| /gem5/src/systemc/tests/systemc/kernel/process_control/test04/ |
| H A D | test04.cpp | 82 void master() function
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| /gem5/ext/systemc/src/tlm_core/tlm_1/tlm_req_rsp/tlm_channels/tlm_req_rsp_channels/ |
| H A D | tlm_req_rsp_channels.h | 95 tlm_master_imp< REQ , RSP > master; member in class:tlm::tlm_req_rsp_channel
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| /gem5/src/systemc/ext/tlm_core/1/req_rsp/channels/req_rsp_channels/ |
| H A D | req_rsp_channels.hh | 87 tlm_master_imp<REQ, RSP> master; member in class:tlm::tlm_req_rsp_channel
|
| /gem5/src/gpu-compute/ |
| H A D | X86GPUTLB.py | 64 master = VectorMasterPort("Port on side closer to memory") variable in class:X86GPUTLB
75 master = VectorMasterPort("Port on side closer to memory") variable in class:TLBCoalescer
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| /gem5/src/mem/ruby/system/ |
| H A D | Sequencer.py | 41 master = VectorMasterPort("CPU master port") variable in class:RubyPort
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| /gem5/ext/sst/ |
| H A D | gem5.cc | 256 auto master = new ExtMaster(this, info, owner, s); local
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| /gem5/src/dev/net/ |
| H A D | dist_iface.hh | 515 static DistIface *master; member in class:DistIface
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| /gem5/src/dev/storage/ |
| H A D | ide_ctrl.hh | 96 IdeDisk *master, *slave; member in struct:IdeController::Channel
|