| /gem5/src/mem/cache/ |
| H A D | noncoherent_cache.cc | 150 createMissPacket(PacketPtr cpu_pkt, CacheBlk *blk, bool needs_writable, bool is_whole_line_write) const argument
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| H A D | queue.hh | 143 bool isEmpty() const argument
148 bool isFull() const argument
153 int numInService() const argument
166 findMatch(Addr blk_addr, bool is_secure, bool ignore_uncacheable = true) const argument
205 findPending(const QueueEntry* entry) const argument
219 getNext() const argument
227 nextReadyTime() const argument
[all...] |
| /gem5/src/mem/cache/prefetch/ |
| H A D | pif.cc | 62 distanceFromTrigger(Addr target, unsigned int log_blk_size) const argument
91 hasAddress(Addr target, unsigned int log_blk_size) const argument
107 getPredictedAddresses(unsigned int log_blk_size, std::vector<AddrPriority> &addresses) const argument
[all...] |
| H A D | queued.hh | 86 bool operator>(const DeferredPacket& that) const argument
90 bool operator<(const DeferredPacket& that) const argument
94 bool operator<=(const DeferredPacket& that) const argument
[all...] |
| H A D | signature_path.hh | 150 inline signature_t updateSignature(signature_t sig, stride_t str) const { argument
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| /gem5/src/mem/cache/tags/ |
| H A D | fa_lru.hh | 128 std::size_t operator()(const std::pair<T1, T2> &p) const argument
[all...] |
| H A D | base.hh | 218 Addr blkAlign(Addr addr) const argument
228 extractBlkOffset(Addr addr) const argument
246 getWayAllocationMax() const argument
[all...] |
| /gem5/src/mem/ |
| H A D | coherent_xbar.hh | 415 isDestination(const PacketPtr pkt) const argument
[all...] |
| H A D | mem_checker_monitor.cc | 335 MemCheckerMonitor::isSnooping() const argument
342 MemCheckerMonitor::getAddrRanges() const argument
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| H A D | external_slave.cc | 178 ExternalSlave::ExternalPort::getAddrRanges() const argument
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| H A D | mem_checker_monitor.hh | 60 const Params* params() const argument
131 bool isSnooping() const argument
187 AddrRangeList getAddrRanges() const argument
[all...] |
| H A D | simple_mem.cc | 230 SimpleMemory::getLatency() const argument
271 SimpleMemory::MemoryPort::getAddrRanges() const argument
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| H A D | serial_link.cc | 120 SerialLink::SerialLinkSlavePort::respQueueFull() const argument
126 SerialLink::SerialLinkMasterPort::reqQueueFull() const argument
423 SerialLink::SerialLinkSlavePort::getAddrRanges() const argument
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| H A D | snoop_filter.hh | 227 snoopAll(Cycles latency) const argument
231 snoopSelected(const SnoopList& slave_ports, Cycles latency) const argument
236 snoopDown(Cycles latency) const argument
325 portToMask(const SlavePort& port) const argument
334 maskToPortList(SnoopMask port_mask) const argument
[all...] |
| /gem5/src/mem/qos/ |
| H A D | mem_sink.cc | 77 MemSinkCtrl::readQueueFull(const uint64_t packets) const argument
83 MemSinkCtrl::writeQueueFull(const uint64_t packets) const argument
351 MemSinkCtrl::MemoryPort::getAddrRanges() const argument
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| /gem5/src/mem/ruby/common/ |
| H A D | Set.hh | 123 int count() const { return bits.count(); } argument
129 isEqual(const Set& obj) const argument
137 OR(const Set& obj) const argument
147 AND(const Se argument
157 intersectionIsEmpty(const Set& obj) const argument
168 isSuperset(const Set& test) const argument
175 isSubset(const Set& test) const argument
177 isElement(NodeID element) const argument
183 isBroadcast() const argument
188 isEmpty() const argument
190 smallestElement() const argument
200 elementAt(int index) const argument
202 getSize() const argument
215 print(std::ostream& out) const argument
[all...] |
| /gem5/src/sim/ |
| H A D | fd_array.cc | 298 FDArray::openFile(std::string const& filename, int flags, mode_t mode) const argument
307 FDArray::openInputFile(std::string const& filename) const argument
313 FDArray::openOutputFile(std::string const& filename) const argument
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| H A D | clocked_object.hh | 82 update() const argument
140 resetClock() const argument
180 clockEdge(Cycles cycles=Cycles(0)) const argument
198 curCycle() const argument
216 Tick nextCycle() const { return clockEdge(Cycles(1)); } argument
218 uint64_t frequency() const { return SimClock::Frequency / clockPeriod(); } argument
220 Tick clockPeriod() const { return clockDomain.clockPeriod(); } argument
222 double voltage() const { return clockDomain.voltage(); } argument
225 ticksToCycles(Tick t) const argument
230 Tick cyclesToTicks(Cycles c) const { retur argument
245 params() const argument
253 pwrState() const argument
256 pwrStateName() const argument
[all...] |
| /gem5/src/arch/arm/insts/ |
| H A D | static_inst.cc | 331 void ArmStaticInst::printPFflags(std::ostream &os, int flag) const argument
57 shift_rm_imm(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const argument
92 shiftReg64(uint64_t base, uint64_t shiftAmt, ArmShiftType type, uint8_t width) const argument
131 extendReg64(uint64_t base, ArmExtendType type, uint64_t shiftAmt, uint8_t width) const argument
177 shift_rm_rs(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const argument
217 shift_carry_imm(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const argument
257 shift_carry_rs(uint32_t base, uint32_t shamt, uint32_t type, uint32_t cfval) const argument
296 printIntReg(std::ostream &os, RegIndex reg_idx, uint8_t opWidth) const argument
342 printFloatReg(std::ostream &os, RegIndex reg_idx) const argument
348 printVecReg(std::ostream &os, RegIndex reg_idx, bool isSveVecReg) const argument
355 printVecPredReg(std::ostream &os, RegIndex reg_idx) const argument
361 printCCReg(std::ostream &os, RegIndex reg_idx) const argument
367 printMiscReg(std::ostream &os, RegIndex reg_idx) const argument
[all...] |
| H A D | sve_macromem.hh | 91 execute(ExecContext *, Trace::InstRecord *) const argument
98 generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
163 execute(ExecContext *, Trace::InstRecord *) const argument
170 generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
235 execute(ExecContext *, Trace::InstRecord *) const argument
242 generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
308 execute(ExecContext *, Trace::InstRecord *) const argument
315 generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
407 execute(ExecContext *, Trace::InstRecord *) const argument
414 generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
511 execute(ExecContext *, Trace::InstRecord *) const argument
518 generateDisassembly(Addr pc, const SymbolTable *symtab) const argument
[all...] |
| /gem5/src/cpu/pred/ |
| H A D | loop_predictor.cc | 87 LoopPredictor::lindex(Addr pc_in, unsigned instShiftAmt) const argument
104 LoopPredictor::finallindex(int index, int lowPcBits, int way) const argument
151 LoopPredictor::calcConf(int index) const argument
171 LoopPredictor::optionalAgeInc() const argument
364 LoopPredictor::getSizeInBits() const argument
113 getLoop(Addr pc, BranchInfo* bi, bool speculative, unsigned instShiftAmt) const argument
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| H A D | tage_sc_l_64KB.cc | 200 TAGE_SC_L_TAGE_64KB::gindex_ext(int index, int bank) const argument
206 TAGE_SC_L_TAGE_64KB::gtag(ThreadID tid, Addr pc, int bank) const argument
84 getIndBiasBank(Addr branch_pc, BranchInfo* bi, int hitBank, int altBank) const argument
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| /gem5/src/arch/generic/ |
| H A D | types.hh | 70 instAddr() const argument
81 nextInstAddr() const argument
92 microPC() const argument
106 operator == (const PCStateBase &opc) const argument
112 operator != (const PCStateBase &opc) const argument
148 Addr pc() const { return _pc; } argument
151 Addr npc() const { retur argument
171 branching() const argument
205 upc() const argument
208 nupc() const argument
212 microPC() const argument
229 branching() const argument
253 operator ==(const UPCState<MachInst> &opc) const argument
261 operator !=(const UPCState<MachInst> &opc) const argument
303 nnpc() const argument
317 branching() const argument
334 operator ==(const DelaySlotPCState<MachInst> &opc) const argument
342 operator !=(const DelaySlotPCState<MachInst> &opc) const argument
383 upc() const argument
386 nupc() const argument
390 microPC() const argument
407 branching() const argument
430 operator ==(const DelaySlotUPCState<MachInst> &opc) const argument
439 operator !=(const DelaySlotUPCState<MachInst> &opc) const argument
[all...] |
| /gem5/src/cpu/minor/ |
| H A D | dyn_inst.cc | 92 MinorDynInst::isLastOpInInst() const argument
99 MinorDynInst::isNoCostInst() const argument
105 MinorDynInst::reportData(std::ostream &os) const argument
183 minorTraceInst(const Named &named_object) const argument
[all...] |
| /gem5/src/mem/ruby/network/ |
| H A D | Network.hh | 81 const Params * params() const argument
88 int getNumNodes() const { return m_nodes; } argument
[all...] |