Lines Matching defs:const

58                                 uint32_t type, uint32_t cfval) const
93 ArmShiftType type, uint8_t width) const
132 uint64_t shiftAmt, uint8_t width) const
178 uint32_t type, uint32_t cfval) const
218 uint32_t type, uint32_t cfval) const
258 uint32_t type, uint32_t cfval) const
297 uint8_t opWidth) const
331 void ArmStaticInst::printPFflags(std::ostream &os, int flag) const
333 const char *flagtoprfop[]= { "PLD", "PLI", "PST", "Reserved"};
334 const char *flagtotarget[] = { "L1", "L2", "L3", "Reserved"};
335 const char *flagtopolicy[] = { "KEEP", "STRM"};
342 ArmStaticInst::printFloatReg(std::ostream &os, RegIndex reg_idx) const
349 bool isSveVecReg) const
355 ArmStaticInst::printVecPredReg(std::ostream &os, RegIndex reg_idx) const
361 ArmStaticInst::printCCReg(std::ostream &os, RegIndex reg_idx) const
367 ArmStaticInst::printMiscReg(std::ostream &os, RegIndex reg_idx) const
375 const std::string &suffix,
378 ConditionCode cond64) const
396 const SymbolTable *symtab) const
415 bool noImplicit) const
477 const SymbolTable *symtab,
478 const std::string &prefix,
479 const Addr addr,
480 const std::string &suffix) const
498 ArmShiftType type) const
559 int64_t shiftAmt) const
592 ArmShiftType type, uint64_t imm) const
622 const SymbolTable *symtab) const
630 ArmStaticInst::softwareBreakpoint32(ExecContext *xc, uint16_t imm) const
632 const auto tc = xc->tcBase();
633 const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
634 const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
648 ArmStaticInst::advSIMDFPAccessTrap64(ExceptionLevel el) const
668 ArmStaticInst::checkFPAdvSIMDTrap64(ThreadContext *tc, CPSR cpsr) const
687 CPSR cpsr, CPACR cpacr) const
689 const ExceptionLevel el = currEL(tc);
701 bool fpexc_check, bool advsimd) const
703 const bool have_virtualization = ArmSystem::haveVirtualization(tc);
704 const bool have_security = ArmSystem::haveSecurity(tc);
705 const bool is_secure = inSecureState(tc);
706 const ExceptionLevel cur_el = currEL(tc);
751 const uint32_t iss = advsimd ? (1 << 5) : 0xA;
777 bool isWfe) const
804 bool isWfe) const
844 bool isWfe) const
876 bool isWfe) const
901 ArmStaticInst::checkSETENDEnabled(ThreadContext *tc, CPSR cpsr) const
934 ExceptionLevel pstateEL) const
953 ExceptionLevel pstateEL) const
972 ArmStaticInst::sveAccessTrap(ExceptionLevel el) const
989 ArmStaticInst::checkSveTrap(ThreadContext *tc, CPSR cpsr) const
991 const ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
1009 ArmStaticInst::checkSveEnabled(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const
1011 const ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
1025 const ExceptionLevel el = opModeToEL((OperatingMode) (uint8_t)spsr.mode);
1026 const uint8_t it = itState(spsr);
1036 const bool itd = el == EL2 ?
1052 const OperatingMode mode = (OperatingMode) (uint8_t)spsr.mode;
1056 const OperatingMode cur_mode = (OperatingMode) (uint8_t)cpsr.mode;
1057 const ExceptionLevel target_el = opModeToEL(mode);
1099 ArmStaticInst::getPSTATEFromPSR(ThreadContext *tc, CPSR cpsr, CPSR spsr) const
1137 const ITSTATE it = getRestoredITBits(tc, spsr);
1155 ExceptionLevel pstateEL) const