Searched defs:CLK (Results 201 - 225 of 451) sorted by relevance

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/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/divide/datatypes/
H A Ddatatypes.h71 datatypes( sc_module_name NAME, sc_clock& CLK, const sc_signal<bool>& RESET, const sc_signal_bool_vector2& IN_VALUE1, const sc_signal_bool_vector2& IN_VALUE2, const sc_signal_bool_vector3& IN_VALUE3, const sc_signal_bool_vector3& IN_VALUE4, const sc_signal<bool>& IN_VALID, sc_signal_bool_vector2& OUT_VALUE1, sc_signal_bool_vector2& OUT_VALUE2, sc_signal_bool_vector3& OUT_VALUE3, sc_signal_bool_vector3& OUT_VALUE4, sc_signal<bool>& OUT_ACK, sc_signal<bool>& OUT_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/bitwidth/
H A Dbitwidth.h71 bitwidth( sc_module_name NAME, sc_clock& CLK, const sc_signal<bool>& RESET, const sc_signal_bool_vector2& IN_VALUE1, const sc_signal_bool_vector4& IN_VALUE2, const sc_signal_bool_vector6& IN_VALUE3, const sc_signal_bool_vector8& IN_VALUE4, const sc_signal<bool>& IN_VALID, sc_signal_bool_vector2& OUT_VALUE1, sc_signal_bool_vector4& OUT_VALUE2, sc_signal_bool_vector6& OUT_VALUE3, sc_signal_bool_vector8& OUT_VALUE4, sc_signal<bool>& OUT_ACK, sc_signal<bool>& OUT_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/arith/subtract/datatypes/
H A Dstimulus.h61 stimulus( sc_module_name NAME, sc_clock& CLK, sc_signal<bool>& RESET, sc_signal_bool_vector& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal<long>& OUT_VALUE3, sc_signal<int>& OUT_VALUE4, sc_signal<short>& OUT_VALUE5, sc_signal<char>& OUT_VALUE6, sc_signal<bool>& OUT_VALID, const sc_signal<bool>& IN_ACK ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/bitwise/and/datatypes/
H A Ddisplay.h62 display( sc_module_name NAME, sc_clock& CLK, const sc_signal_bool_vector8& IN_VALUE1, const sc_signal_bool_vector8& IN_VALUE2, const sc_signal<long>& IN_VALUE3, const sc_signal<int>& IN_VALUE4, const sc_signal<short>& IN_VALUE5, const sc_signal<char>& IN_VALUE6, const sc_signal<bool>& IN_VALUE7, const sc_signal_bool_vector4& IN_VALUE8, const sc_signal_logic_vector4& IN_VALUE9, const sc_signal<bool>& IN_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/bitwise/not/datatypes/
H A Ddisplay.h62 display( sc_module_name NAME, sc_clock& CLK, const sc_signal_bool_vector8& IN_VALUE1, const sc_signal_bool_vector8& IN_VALUE2, const sc_signal<long>& IN_VALUE3, const sc_signal<int>& IN_VALUE4, const sc_signal<short>& IN_VALUE5, const sc_signal<char>& IN_VALUE6, const sc_signal<bool>& IN_VALUE7, const sc_signal_bool_vector4& IN_VALUE8, const sc_signal_logic_vector4& IN_VALUE9, const sc_signal<bool>& IN_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/bitwise/or/datatypes/
H A Dstimulus.h62 stimulus( sc_module_name NAME, sc_clock& CLK, sc_signal<bool>& RESET, sc_signal_bool_vector& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal<long>& OUT_VALUE3, sc_signal<int>& OUT_VALUE4, sc_signal<short>& OUT_VALUE5, sc_signal<char>& OUT_VALUE6, sc_signal<char>& OUT_VALUE7, sc_signal<bool>& OUT_VALID, const sc_signal<bool>& IN_ACK ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/datatypes/
H A Dstimulus.h61 stimulus( sc_module_name NAME, sc_clock& CLK, sc_signal<bool>& RESET, sc_signal_bool_vector& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal<long>& OUT_VALUE3, sc_signal<int>& OUT_VALUE4, sc_signal<short>& OUT_VALUE5, sc_signal<char>& OUT_VALUE6, sc_signal<bool>& OUT_VALID, const sc_signal<bool>& IN_ACK ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shl/sharing/
H A Dstimulus.h61 stimulus( sc_module_name NAME, sc_clock& CLK, sc_signal<bool>& RESET, sc_signal_bool_vector& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal<long>& OUT_VALUE3, sc_signal<int>& OUT_VALUE4, sc_signal<short>& OUT_VALUE5, sc_signal<char>& OUT_VALUE6, sc_signal<bool>& OUT_VALID, const sc_signal<bool>& IN_ACK ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/bitwise/shr/sharing/
H A Dstimulus.h61 stimulus( sc_module_name NAME, sc_clock& CLK, sc_signal<bool>& RESET, sc_signal_bool_vector& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal<long>& OUT_VALUE3, sc_signal<int>& OUT_VALUE4, sc_signal<short>& OUT_VALUE5, sc_signal<char>& OUT_VALUE6, sc_signal<bool>& OUT_VALID, const sc_signal<bool>& IN_ACK ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/bitwise/xor/datatypes/
H A Ddisplay.h62 display( sc_module_name NAME, sc_clock& CLK, const sc_signal_bool_vector8& IN_VALUE1, const sc_signal_bool_vector8& IN_VALUE2, const sc_signal<long>& IN_VALUE3, const sc_signal<int>& IN_VALUE4, const sc_signal<short>& IN_VALUE5, const sc_signal<char>& IN_VALUE6, const sc_signal<bool>& IN_VALUE7, const sc_signal_bool_vector4& IN_VALUE8, const sc_signal_logic_vector4& IN_VALUE9, const sc_signal<bool>& IN_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/control/case/balancing/
H A Dbalancing.h63 balancing( sc_module_name NAME, sc_clock& CLK, const sc_signal<bool>& RESET, const sc_signal_bool_vector& IN_VALUE1, const sc_signal_bool_vector& IN_VALUE2, const sc_signal_bool_vector& IN_VALUE3, const sc_signal<bool>& IN_VALID, sc_signal_bool_vector& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal_bool_vector& OUT_VALUE3, sc_signal<bool>& OUT_VALID1, sc_signal<bool>& OUT_VALID2, sc_signal<bool>& OUT_VALID3 ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/control/case/datatypes/
H A Ddatatypes.h63 datatypes( sc_module_name NAME, sc_clock& CLK, const sc_signal<bool>& RESET, const sc_signal_bool_vector& IN_VALUE1, const sc_signal_bool_vector& IN_VALUE2, const sc_signal_bool_vector& IN_VALUE3, const sc_signal_bool_vector& IN_VALUE4, const sc_signal<bool>& IN_VALID, sc_signal_bool_vector& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal_bool_vector& OUT_VALUE3, sc_signal_bool_vector& OUT_VALUE4, sc_signal<bool>& OUT_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/control/case/fsm/
H A Dfsm.h63 fsm( sc_module_name NAME, sc_clock& CLK, const sc_signal<bool>& RESET, const sc_signal_bool_vector& IN_VALUE1, const sc_signal_bool_vector& IN_VALUE2, const sc_signal_bool_vector& IN_VALUE3, const sc_signal<bool>& IN_VALID, sc_signal_bool_vector& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal_bool_vector& OUT_VALUE3, sc_signal<bool>& OUT_VALID1, sc_signal<bool>& OUT_VALID2, sc_signal<bool>& OUT_VALID3 ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/control/case/inlining/
H A Dinlining.h61 inlining( sc_module_name NAME, sc_clock& CLK, const sc_signal<bool>& RESET, const sc_signal_bool_vector& IN_VALUE1, const sc_signal_bool_vector& IN_VALUE2, const sc_signal_bool_vector& IN_VALUE3, const sc_signal_bool_vector& IN_VALUE4, const sc_signal<bool>& IN_VALID, sc_signal_bool_vector& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal<bool>& OUT_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/balancing/
H A Dbalancing.h63 balancing( sc_module_name NAME, sc_clock& CLK, const sc_signal<bool>& RESET, const sc_signal_bool_vector& IN_VALUE1, const sc_signal_bool_vector& IN_VALUE2, const sc_signal_bool_vector& IN_VALUE3, const sc_signal<bool>& IN_VALID, sc_signal_bool_vector& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal_bool_vector& OUT_VALUE3, sc_signal<bool>& OUT_VALID1, sc_signal<bool>& OUT_VALID2, sc_signal<bool>& OUT_VALID3 ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/datatypes/
H A Ddatatypes.h63 datatypes( sc_module_name NAME, sc_clock& CLK, const sc_signal<bool>& RESET, const sc_signal_bool_vector& IN_VALUE1, const sc_signal_bool_vector& IN_VALUE2, const sc_signal_bool_vector& IN_VALUE3, const sc_signal_bool_vector& IN_VALUE4, const sc_signal<bool>& IN_VALID, sc_signal_bool_vector& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal_bool_vector& OUT_VALUE3, sc_signal_bool_vector& OUT_VALUE4, sc_signal<bool>& OUT_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/fsm/
H A Dfsm.h63 fsm( sc_module_name NAME, sc_clock& CLK, const sc_signal<bool>& RESET, const sc_signal_bool_vector& IN_VALUE1, const sc_signal_bool_vector& IN_VALUE2, const sc_signal_bool_vector& IN_VALUE3, const sc_signal<bool>& IN_VALID, sc_signal_bool_vector& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal_bool_vector& OUT_VALUE3, sc_signal<bool>& OUT_VALID1, sc_signal<bool>& OUT_VALID2, sc_signal<bool>& OUT_VALID3 ) argument
/gem5/src/systemc/tests/systemc/misc/cae_test/general/control/if_test/inlining/
H A Dinlining.h61 inlining( sc_module_name NAME, sc_clock& CLK, const sc_signal<bool>& RESET, const sc_signal_bool_vector& IN_VALUE1, const sc_signal_bool_vector& IN_VALUE2, const sc_signal_bool_vector& IN_VALUE3, const sc_signal_bool_vector& IN_VALUE4, const sc_signal<bool>& IN_VALID, sc_signal_bool_vector& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal<bool>& OUT_VALID ) argument
/gem5/src/systemc/tests/systemc/misc/communication/channel/dataflow/
H A Ddataflow.cpp49 sawtooth( sc_module_name NAME, sc_clock& CLK, sc_fifo<int>& OUT1, sc_fifo<int>& OUT2 ) argument
83 delay( sc_module_name NAME, sc_clock& CLK, sc_fifo<int>& IN_, sc_fifo<int>& OUT_ ) argument
116 downsample( sc_module_name NAME, sc_clock& CLK, sc_fifo<int>& IN_, sc_fifo<int>& OUT_ ) argument
149 upsample( sc_module_name NAME, sc_clock& CLK, sc_fifo<int>& IN_, sc_fifo<int>& OUT_ ) argument
180 adder( sc_module_name NAME, sc_clock& CLK, sc_fifo<int>& A, sc_fifo<int>& B ) argument
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/gem5/src/systemc/tests/systemc/misc/communication/channel/hwsw/
H A Dhwsw.cpp60 adder_sub( sc_module_name NAME, sc_clock& CLK, sc_fifo<int>& SA, sc_fifo<int>& SB, sc_fifo<int>& SC, sc_fifo<int>& SD, sc_fifo<int>& SSUM ) argument
121 testbench( sc_module_name NAME, sc_clock& CLK, sc_fifo<int>& SSUM, sc_fifo<int>& SDIFF, sc_fifo<int>& SA, sc_fifo<int>& SB, sc_fifo<int>& SC ) argument
/gem5/src/systemc/tests/systemc/misc/examples/a2901/
H A Da2901_edge.h48 const sc_clock& CLK; local
/gem5/src/systemc/tests/systemc/misc/sim_tests/popc/
H A Dpopc.cpp59 proc1( sc_module_name NAME, sc_clock& CLK, sc_signal<bool>& DATA_ACK, sc_signal<int>& POPC, sc_signal<bool>& RESET, sc_signal<bool>& DATA_READY, sc_signal<int>& IN_ ) argument
101 proc2( sc_module_name NAME, sc_clock& CLK, sc_signal<bool>& RESET, sc_signal<bool>& DATA_READY, sc_signal<int>& IN_, sc_signal<bool>& DATA_ACK, sc_signal<int>& POPC ) argument
/gem5/src/systemc/tests/systemc/misc/stars/star110069/
H A Dmem0.h67 mem0( sc_module_name NAME, sc_clock& CLK, const sc_signal<bool>& RESET, const sc_signal_bool_vector& IN_VALUE1, const sc_signal_bool_vector& IN_VALUE2, const sc_signal<bool>& IN_VALID, sc_signal_bool_vector& OUT_VALUE1, sc_signal_bool_vector& OUT_VALUE2, sc_signal<bool>& OUT_VALID, int *MEMORY ) argument
/gem5/src/systemc/tests/systemc/misc/synth/directives/line_label/misc/test1/
H A Dinterface.h63 t( sc_module_name NAME, sc_clock& CLK, const sc_signal<bool>& RESET_SIG, const sc_signal<int>& I1, const sc_signal<int>& I2, const sc_signal<int>& I3, const sc_signal<int>& I4, const sc_signal<int>& I5, sc_signal<int>& O1, sc_signal<int>& O2, sc_signal<int>& O3, sc_signal<int>& O4, sc_signal<int>& O5) argument
/gem5/src/systemc/tests/systemc/misc/synth/directives/line_label/misc/test2/
H A Dinterface.h63 t( sc_module_name NAME, sc_clock& CLK, const sc_signal<bool>& RESET_SIG, const sc_signal<int>& I1, const sc_signal<int>& I2, const sc_signal<int>& I3, const sc_signal<int>& I4, const sc_signal<int>& I5, sc_signal<int>& O1, sc_signal<int>& O2, sc_signal<int>& O3, sc_signal<int>& O4, sc_signal<int>& O5) argument

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