tests/configs/pc-simple-timing-ruby.py

53 #the system
55 system = FSConfig.makeLinuxX86System('timing', options.num_cpus,
57 system.kernel = SysPaths.binary('x86_64-vmlinux-2.6.22.9')
59 system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
61 system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp')
62 system.clk_domain = SrcClockDomain(clock = '1GHz',
63                                    voltage_domain = system.voltage_domain)
64 system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
65                                        voltage_domain = system.voltage_domain)
66 system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain)
69 Ruby.create_system(options, True, system, system.iobus, system._dma_ports)
72 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
73                                         voltage_domain = system.voltage_domain)
77 system.iobus.master = system.ruby._io_port.slave
79 for (i, cpu) in enumerate(system.cpu):
82     # Tie the cpu ports to the correct ruby system ports
83     cpu.icache_port = system.ruby._cpu_ports[i].slave
84     cpu.dcache_port = system.ruby._cpu_ports[i].slave
85     cpu.itb.walker.port = system.ruby._cpu_ports[i].slave
86     cpu.dtb.walker.port = system.ruby._cpu_ports[i].slave
88     cpu.interrupts[0].pio = system.ruby._cpu_ports[i].master
89     cpu.interrupts[0].int_master = system.ruby._cpu_ports[i].slave
90     cpu.interrupts[0].int_slave = system.ruby._cpu_ports[i].master
92 root = Root(full_system = True, system = system)