Lines Matching refs:self
108 def createThreads(self):
111 def createInterruptController(self):
114 def connectCachedPorts(self, bus):
115 if hasattr(self, '_cached_ports') and (len(self._cached_ports) > 0):
116 for p in self._cached_ports:
117 exec('self.%s = bus.slave' % p)
119 self.port = bus.slave
121 def connectAllPorts(self, cached_bus, uncached_bus = None):
122 self.connectCachedPorts(cached_bus)
124 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
125 self.dcache = dc
126 self.port = dc.cpu_side
127 self._cached_ports = ['dcache.mem_side']
128 self._uncached_ports = []