cpu/o3/thread_context.hh

105     int cpuId() const override { return cpu->cpuId(); }
108     uint32_t socketId() const override { return cpu->socketId(); }
110     ContextID contextId() const override { return thread->contextId(); }
115     int threadId() const override { return thread->threadId(); }
144     Status status() const override { return thread->status(); }
171     void regStats(const std::string &name) override;
197     readIntReg(RegIndex reg_idx) const override
204     readFloatReg(RegIndex reg_idx) const override
210     const VecRegContainer &
211     readVecReg(const RegId& id) const override
220     getWritableVecReg(const RegId& id) override
229     readVec8BitLaneReg(const RegId& id) const override
237     readVec16BitLaneReg(const RegId& id) const override
245     readVec32BitLaneReg(const RegId& id) const override
253     readVec64BitLaneReg(const RegId& id) const override
261     setVecLane(const RegId& reg,
262                const LaneData<LaneSize::Byte>& val) override
267     setVecLane(const RegId& reg,
268                const LaneData<LaneSize::TwoByte>& val) override
273     setVecLane(const RegId& reg,
274                const LaneData<LaneSize::FourByte>& val) override
279     setVecLane(const RegId& reg,
280                const LaneData<LaneSize::EightByte>& val) override
286     const VecElem &
287     readVecElem(const RegId& reg) const override
292     const VecPredRegContainer &
293     readVecPredReg(const RegId& id) const override
299     getWritableVecPredReg(const RegId& id) override
305     readCCReg(RegIndex reg_idx) const override
326     setVecReg(const RegId& reg, const VecRegContainer& val) override
332     setVecElem(const RegId& reg, const VecElem& val) override
338     setVecPredReg(const RegId& reg,
339                   const VecPredRegContainer& val) override
352     pcState() const override
358     void pcState(const TheISA::PCState &val) override;
360     void pcStateNoRecord(const TheISA::PCState &val) override;
364     instAddr() const override
371     nextInstAddr() const override
378     microPC() const override
385     readMiscRegNoEffect(RegIndex misc_reg) const override
405     RegId flattenRegId(const RegId& regId) const override;
410     readStCondFailures() const override
430     Counter readFuncExeInst() const override { return thread->funcExeInst; }
450     RegVal readIntRegFlat(RegIndex idx) const override;
453     RegVal readFloatRegFlat(RegIndex idx) const override;
456     const VecRegContainer& readVecRegFlat(RegIndex idx) const override;
459     void setVecRegFlat(RegIndex idx, const VecRegContainer& val) override;
463     readVecLaneFlat(RegIndex idx, int lId) const
471     setVecLaneFlat(int idx, int lId, const LD& val)
476     const VecElem &readVecElemFlat(RegIndex idx,
477                                    const ElemIndex& elemIndex) const override;
478     void setVecElemFlat(RegIndex idx, const ElemIndex& elemIdx,
479                         const VecElem& val) override;
481     const VecPredRegContainer& readVecPredRegFlat(RegIndex idx) const override;
484                            const VecPredRegContainer& val) override;
486     RegVal readCCRegFlat(RegIndex idx) const override;