src/cpu/base_dyn_inst.hh

154     const StaticInstPtr staticInst;
204     const StaticInstPtr macroop;
276     bool effAddrValid() const { return instFlags[EffAddrValid]; }
280     bool memOpDone() const { return instFlags[MemOpDone]; }
283     bool notAnInst() const { return instFlags[NotAnInst]; }
307             const std::vector<bool>& byteEnable = std::vector<bool>());
311                    const std::vector<bool>& byteEnable = std::vector<bool>());
317     bool translationStarted() const { return instFlags[TranslationStarted]; }
321     bool translationCompleted() const { return instFlags[TranslationCompleted]; }
329     bool possibleLoadViolation() const { return instFlags[PossibleLoadViolation]; }
336     bool hitExternalSnoop() const { return instFlags[HitExternalSnoop]; }
343     bool isTranslationDelayed() const
356     PhysRegIdPtr renamedDestRegIdx(int idx) const
362     PhysRegIdPtr renamedSrcRegIdx(int idx) const
371     const RegId& flattenedDestRegIdx(int idx) const
379     PhysRegIdPtr prevDestRegIdx(int idx) const
409     void flattenDestReg(int idx, const RegId& flattened_dest)
420     BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop,
427     BaseDynInst(const StaticInstPtr &staticInst, const StaticInstPtr &macroop);
444     int cpuId() const { return cpu->cpuId(); }
447     uint32_t socketId() const { return cpu->socketId(); }
450     MasterID masterId() const { return cpu->dataMasterId(); }
453     ContextID contextId() const { return thread->contextId(); }
456     Fault getFault() const { return fault; }
469     void setPredTarg(const TheISA::PCState &_predPC)
474     const TheISA::PCState &readPredTarg() { return predPC; }
507     bool isNop()          const { return staticInst->isNop(); }
508     bool isMemRef()       const { return staticInst->isMemRef(); }
509     bool isLoad()         const { return staticInst->isLoad(); }
510     bool isStore()        const { return staticInst->isStore(); }
511     bool isAtomic()       const { return staticInst->isAtomic(); }
512     bool isStoreConditional() const
514     bool isInstPrefetch() const { return staticInst->isInstPrefetch(); }
515     bool isDataPrefetch() const { return staticInst->isDataPrefetch(); }
516     bool isInteger()      const { return staticInst->isInteger(); }
517     bool isFloating()     const { return staticInst->isFloating(); }
518     bool isVector()       const { return staticInst->isVector(); }
519     bool isControl()      const { return staticInst->isControl(); }
520     bool isCall()         const { return staticInst->isCall(); }
521     bool isReturn()       const { return staticInst->isReturn(); }
522     bool isDirectCtrl()   const { return staticInst->isDirectCtrl(); }
523     bool isIndirectCtrl() const { return staticInst->isIndirectCtrl(); }
524     bool isCondCtrl()     const { return staticInst->isCondCtrl(); }
525     bool isUncondCtrl()   const { return staticInst->isUncondCtrl(); }
526     bool isCondDelaySlot() const { return staticInst->isCondDelaySlot(); }
527     bool isThreadSync()   const { return staticInst->isThreadSync(); }
528     bool isSerializing()  const { return staticInst->isSerializing(); }
529     bool isSerializeBefore() const
531     bool isSerializeAfter() const
533     bool isSquashAfter() const { return staticInst->isSquashAfter(); }
534     bool isMemBarrier()   const { return staticInst->isMemBarrier(); }
535     bool isWriteBarrier() const { return staticInst->isWriteBarrier(); }
536     bool isNonSpeculative() const { return staticInst->isNonSpeculative(); }
537     bool isQuiesce() const { return staticInst->isQuiesce(); }
538     bool isIprAccess() const { return staticInst->isIprAccess(); }
539     bool isUnverifiable() const { return staticInst->isUnverifiable(); }
540     bool isSyscall() const { return staticInst->isSyscall(); }
541     bool isMacroop() const { return staticInst->isMacroop(); }
542     bool isMicroop() const { return staticInst->isMicroop(); }
543     bool isDelayedCommit() const { return staticInst->isDelayedCommit(); }
544     bool isLastMicroop() const { return staticInst->isLastMicroop(); }
545     bool isFirstMicroop() const { return staticInst->isFirstMicroop(); }
546     bool isMicroBranch() const { return staticInst->isMicroBranch(); }
577     OpClass opClass() const { return staticInst->opClass(); }
580     TheISA::PCState branchTarget() const
584     int8_t numSrcRegs() const { return staticInst->numSrcRegs(); }
587     int8_t numDestRegs() const { return staticInst->numDestRegs(); }
591     int8_t numFPDestRegs()  const { return staticInst->numFPDestRegs(); }
592     int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
593     int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); }
594     int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); }
595     int8_t numVecElemDestRegs() const
600     numVecPredDestRegs() const
606     const RegId& destRegIdx(int i) const { return staticInst->destRegIdx(i); }
609     const RegId& srcRegIdx(int i) const { return staticInst->srcRegIdx(i); }
671     void setIntRegOperand(const StaticInst *si, int idx, RegVal val)
677     void setCCRegOperand(const StaticInst *si, int idx, RegVal val)
683     void setVecRegOperand(const StaticInst *si, int idx,
684             const VecRegContainer& val)
691     setFloatRegOperandBits(const StaticInst *si, int idx, RegVal val)
697     void setVecElemOperand(const StaticInst *si, int idx, const VecElem val)
703     void setVecPredRegOperand(const StaticInst *si, int idx,
704                               const VecPredRegContainer& val)
716     bool isReadySrcRegIdx(int idx) const
725     bool isCompleted() const { return status[Completed]; }
731     bool isResultReady() const { return status[ResultReady]; }
737     bool readyToIssue() const { return status[CanIssue]; }
746     bool isIssued() const { return status[Issued]; }
755     bool isExecuted() const { return status[Executed]; }
764     bool readyToCommit() const { return status[CanCommit]; }
774     bool isCommitted() const { return status[Committed]; }
780     bool isSquashed() const { return status[Squashed]; }
791     bool isInIQ() const { return status[IqEntry]; }
797     bool isSquashedInIQ() const { return status[SquashedInIQ]; }
809     bool isInLSQ() const { return status[LsqEntry]; }
815     bool isSquashedInLSQ() const { return status[SquashedInLSQ]; }
827     bool isInROB() const { return status[RobEntry]; }
833     bool isSquashedInROB() const { return status[SquashedInROB]; }
836     bool isPinnedRegsRenamed() const { return status[PinnedRegsRenamed]; }
848     bool isPinnedRegsWritten() const { return status[PinnedRegsWritten]; }
861     isPinnedRegsSquashDone() const { return status[PinnedRegsSquashDone]; }
871     TheISA::PCState pcState() const { return pc; }
874     void pcState(const TheISA::PCState &val) { pc = val; }
877     Addr instAddr() const { return pc.instAddr(); }
880     Addr nextInstAddr() const { return pc.nextInstAddr(); }
883     Addr microPC() const { return pc.microPC(); }
885     bool readPredicate() const
900     readMemAccPredicate() const
926     bool eaSrcsReady() const;
929     bool strictlyOrdered() const { return instFlags[IsStrictlyOrdered]; }
933     bool hasRequest() const { return instFlags[ReqMade]; }
945     unsigned int readStCondFailures() const
966                                    const std::vector<bool>& byteEnable)
978                             const std::vector<bool>& byteEnable)