arch/sparc/tlb.cc

419 TLB::translateInst(const RequestPtr &req, ThreadContext *tc)
421     uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
533 TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
539     uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
837 TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
840         return translateInst(req, tc);
842         return translateData(req, tc, mode == Write);
846 TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
850     translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
855                       ThreadContext *tc, Mode mode) const
861 TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
870     TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
875         pkt->setBE(tc->readMiscReg(MISCREG_MMU_LSU_CTRL));
880             pkt->setBE(tc->readMiscReg(MISCREG_MMU_P_CONTEXT));
883             pkt->setBE(tc->readMiscReg(MISCREG_MMU_S_CONTEXT));
890         pkt->setBE(tc->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
946         pkt->setBE(tc->readMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
980             pkt->setBE(tc->readMiscReg(MISCREG_MMU_PART_ID));
1022                         tc->getCpuPtr()->getInterruptController(0));
1030                         tc->getCpuPtr()->getInterruptController(0));
1032             tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, temp);
1046 TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
1066     TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
1071         tc->setMiscReg(MISCREG_MMU_LSU_CTRL, data);
1076             tc->setMiscReg(MISCREG_MMU_P_CONTEXT, data);
1079             tc->setMiscReg(MISCREG_MMU_S_CONTEXT, data);
1087         tc->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD +
1144         tc->setMiscReg(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1167         part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
1182         part_insert = tc->readMiscReg(MISCREG_MMU_PART_ID);
1192         part_id =  tc->readMiscReg(MISCREG_MMU_PART_ID);
1195             ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
1233             tc->setMiscReg(MISCREG_MMU_PART_ID, data);
1242         part_id =  tc->readMiscReg(MISCREG_MMU_PART_ID);
1245             ctx_id = tc->readMiscReg(MISCREG_MMU_P_CONTEXT);
1248             ctx_id = tc->readMiscReg(MISCREG_MMU_S_CONTEXT);
1279                         tc->getCpuPtr()->getInterruptController(0));
1282                 tc->getCpuPtr()->clearInterrupt(0, IT_INT_VEC, msb);
1287             tc->getSystemPtr()->threadContexts[bits(data,12,8)]->getCpuPtr()->
1300 TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
1303     TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());