arch/sparc/tlb.cc

35 #include "arch/sparc/asi.hh"
383 TLB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi)
396     sfsr |= asi << 16;
410         bool se, FaultTypes ft, int asi)
412     DPRINTF(TLB, "TLB: Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
413             a, (int)write, ct, ft, asi);
414     TLB::writeSfsr(write, ct, se, ft, asi);
456     int asi;
463         asi = ASI_N;
467         asi = ASI_P;
482         writeSfsr(false, ct, false, OtherFault, asi);
490         writeSfsr(false, ct, false, VaOutOfRange, asi);
518         writeSfsr(false, ct, false, PrivViolation, asi);
542     ASI asi;
543     asi = (ASI)req->getArchFlags();
548     DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
549             vaddr, size, asi);
554     if (asi == ASI_IMPLICIT)
573                 if (cacheAsi[0] == asi &&
588                 if (cacheAsi[1] == asi &&
624             asi = ASI_N;
628             asi = ASI_P;
633         // We need to check for priv level/asi priv
634         if (!priv && !hpriv && !asiIsUnPriv(asi)) {
636             writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi);
640         if (!hpriv && asiIsHPriv(asi)) {
641             writeSfsr(vaddr, write, Nucleus, false, IllegalAsi, asi);
645         if (asiIsPrimary(asi)) {
648         } else if (asiIsSecondary(asi)) {
651         } else if (asiIsNucleus(asi)) {
660     if (!implicit && asi != ASI_P && asi != ASI_S) {
661         if (asiIsLittle(asi))
667 //        if (asiIsNoFault(asi))
670         if (asiIsPartialStore(asi))
673         if (asiIsCmt(asi))
676         if (asiIsInterrupt(asi))
678         if (asiIsMmu(asi))
680         if (asiIsScratchPad(asi))
682         if (asiIsQueue(asi))
684         if (asiIsSparcError(asi))
687         if (!asiIsReal(asi) && !asiIsNucleus(asi) && !asiIsAsIfUser(asi) &&
688                 !asiIsTwin(asi) && !asiIsBlock(asi) && !asiIsNoFault(asi))
689             panic("Accessing ASI %#X. Should we?\n", asi);
692     // If the asi is unaligned trap
694         writeSfsr(vaddr, false, ct, false, OtherFault, asi);
702         writeSfsr(vaddr, false, ct, true, VaOutOfRange, asi);
706     if ((!lsu_dm && !hpriv && !red) || asiIsReal(asi)) {
711     if (hpriv && (implicit || (!asiIsAsIfUser(asi) && !asiIsReal(asi)))) {
735         writeSfsr(vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
741         writeSfsr(vaddr, write, ct, e->pte.sideffect(), OtherFault, asi);
745     if (e->pte.nofault() && !asiIsNoFault(asi)) {
747         writeSfsr(vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi);
751     if (e->pte.sideffect() && asiIsNoFault(asi)) {
753         writeSfsr(vaddr, write, ct, e->pte.sideffect(), SideEffect, asi);
771         cacheAsi[0] = asi;
783         writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
790     if ((asi == ASI_SWVR_UDB_INTR_W && !write) ||
791         (asi == ASI_SWVR_UDB_INTR_R && write)) {
792         writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
801         writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
808         writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
812         writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
819         writeSfsr(vaddr, write, Primary, true, IllegalAsi, asi);
864     ASI asi = (ASI)pkt->req->getArchFlags();
867     DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
872     switch (asi) {
1038         panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1039             (uint32_t)asi, va);
1050     ASI asi = (ASI)pkt->req->getArchFlags();
1063     DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1064          (uint32_t)asi, va, data);
1068     switch (asi) {
1292         panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",