arch/sparc/tlb.cc

45 #include "debug/TLB.hh"
55 TLB::TLB(const Params *p)
61         fatal("SPARC T1 TLB registers don't support more than 64 TLB entries");
83 TLB::clearUsedBits()
97 TLB::insert(Addr va, int partition_id, int context_id, bool real,
114     DPRINTF(TLB,
115         "TLB: Inserting Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
128                 DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x);
198 TLB::lookup(Addr va, int partition_id, bool real, int context_id,
205     DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
217         DPRINTF(TLB, "TLB: No valid entry found\n");
223     DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(),
242 TLB::dumpAll()
256 TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
261     DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
276         DPRINTF(IPR, "TLB: Demapped page\n");
288 TLB::demapContext(int partition_id, int context_id)
290     DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n",
310 TLB::demapAll(int partition_id)
312     DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id);
329 TLB::flushAll()
344 TLB::TteRead(int entry)
357 TLB::TagRead(int entry)
373 TLB::validVirtualAddress(Addr va, bool am)
383 TLB::writeSfsr(bool write, ContextType ct, bool se, FaultTypes ft, int asi)
400 TLB::writeTagAccess(Addr va, int context)
402     DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
409 TLB::writeSfsr(Addr a, bool write, ContextType ct,
412     DPRINTF(TLB, "TLB: Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
414     TLB::writeSfsr(write, ct, se, ft, asi);
419 TLB::translateInst(const RequestPtr &req, ThreadContext *tc)
428     DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
459     DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
528     DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
533 TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
548     DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
581                     DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
596                     DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
619     DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
720         DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
777     DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
830     DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
837 TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
846 TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
854 TLB::finalizePhysical(const RequestPtr &req,
861 TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
870     TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
1046 TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
1066     TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
1300 TLB::GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs)
1303     TLB *itb = dynamic_cast<TLB *>(tc->getITBPtr());
1327 TLB::MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
1354 TLB::serialize(CheckpointOut &cp) const
1384 TLB::unserialize(CheckpointIn &cp)
1422 SparcISA::TLB *
1425     return new SparcISA::TLB(this);