Lines Matching refs:self
61 def __init__(self, options=None):
62 super(L1Cache, self).__init__()
65 def connectBus(self, bus):
67 self.mem_side = bus.slave
69 def connectCPU(self, cpu):
83 def __init__(self, opts=None):
84 super(L1ICache, self).__init__(opts)
87 self.size = opts.l1i_size
89 def connectCPU(self, cpu):
91 self.cpu_side = cpu.icache_port
102 def __init__(self, opts=None):
103 super(L1DCache, self).__init__(opts)
106 self.size = opts.l1d_size
108 def connectCPU(self, cpu):
110 self.cpu_side = cpu.dcache_port
126 def __init__(self, opts=None):
127 super(L2Cache, self).__init__()
130 self.size = opts.l2_size
132 def connectCPUSideBus(self, bus):
133 self.cpu_side = bus.master
135 def connectMemSideBus(self, bus):
136 self.mem_side = bus.slave