example/arm/devices.py

113     def __init__(self, system,  num_cpus, cpu_clock, cpu_voltage,
115         super(CpuCluster, self).__init__()
116         self._cpu_type = cpu_type
117         self._l1i_type = l1i_type
118         self._l1d_type = l1d_type
119         self._wcache_type = wcache_type
120         self._l2_type = l2_type
124         self.voltage_domain = VoltageDomain(voltage=cpu_voltage)
125         self.clk_domain = SrcClockDomain(clock=cpu_clock,
126                                          voltage_domain=self.voltage_domain)
128         self.cpus = [ self._cpu_type(cpu_id=system.numCpus() + idx,
129                                      clk_domain=self.clk_domain)
132         for cpu in self.cpus:
136         system.addCpuCluster(self, num_cpus)
138     def requireCaches(self):
139         return self._cpu_type.require_caches()
141     def memoryMode(self):
142         return self._cpu_type.memory_mode()
144     def addL1(self):
145         for cpu in self.cpus:
146             l1i = None if self._l1i_type is None else self._l1i_type()
147             l1d = None if self._l1d_type is None else self._l1d_type()
148             iwc = None if self._wcache_type is None else self._wcache_type()
149             dwc = None if self._wcache_type is None else self._wcache_type()
152     def addL2(self, clk_domain):
153         if self._l2_type is None:
155         self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain)
156         self.l2 = self._l2_type()
157         for cpu in self.cpus:
158             cpu.connectAllPorts(self.toL2Bus)
159         self.toL2Bus.master = self.l2.cpu_side
161     def connectMemSide(self, bus):
164             self.l2.mem_side = bus.slave
166             for cpu in self.cpus:
171     def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
173         super(AtomicCluster, self).__init__(system, num_cpus, cpu_clock,
175     def addL1(self):
179     def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
181         super(KvmCluster, self).__init__(system, num_cpus, cpu_clock,
183     def addL1(self):
190     def __init__(self, caches, mem_size, platform=None, **kwargs):
191         super(SimpleSystem, self).__init__(**kwargs)
193         self.voltage_domain = VoltageDomain(voltage="1.0V")
194         self.clk_domain = SrcClockDomain(clock="1GHz",
198             self.realview = VExpress_GEM5_V1()
200             self.realview = platform
202         if hasattr(self.realview.gic, 'cpu_addr'):
203             self.gic_cpu_addr = self.realview.gic.cpu_addr
204         self.flags_addr = self.realview.realview_io.pio_addr + 0x30
206         self.membus = MemBus()
208         self.intrctrl = IntrControl()
209         self.terminal = Terminal()
210         self.vncserver = VncServer()
212         self.iobus = IOXBar()
214         self.iobridge = Bridge(delay='50ns')
216         mem_range = self.realview._mem_regions[0]
218         self.mem_ranges = [ AddrRange(start=mem_range.start, size=mem_size) ]
219         self._caches = caches
220         if self._caches:
221             self.iocache = IOCache(addr_ranges=[self.mem_ranges[0]])
223             self.dmabridge = Bridge(delay='50ns',
224                                     ranges=[self.mem_ranges[0]])
226         self._pci_devices = 0
227         self._clusters = []
228         self._num_cpus = 0
230     def attach_pci(self, dev):
231         dev.pci_bus, dev.pci_dev, dev.pci_func = (0, self._pci_devices + 1, 0)
232         self._pci_devices += 1
233         self.realview.attachPciDevice(dev, self.iobus)
235     def connect(self):
236         self.iobridge.master = self.iobus.slave
237         self.iobridge.slave = self.membus.master
239         if self._caches:
240             self.iocache.mem_side = self.membus.slave
241             self.iocache.cpu_side = self.iobus.master
243             self.dmabridge.master = self.membus.slave
244             self.dmabridge.slave = self.iobus.master
246         if hasattr(self.realview.gic, 'cpu_addr'):
247             self.gic_cpu_addr = self.realview.gic.cpu_addr
248         self.realview.attachOnChipIO(self.membus, self.iobridge)
249         self.realview.attachIO(self.iobus)
250         self.system_port = self.membus.slave
252     def numCpuClusters(self):
253         return len(self._clusters)
255     def addCpuCluster(self, cpu_cluster, num_cpus):
256         assert cpu_cluster not in self._clusters
258         self._clusters.append(cpu_cluster)
259         self._num_cpus += num_cpus
261     def numCpus(self):
262         return self._num_cpus
264     def addCaches(self, need_caches, last_cache_level):
267             for cluster in self._clusters:
268                 cluster.connectMemSide(self.membus)
271         cluster_mem_bus = self.membus
273         for cluster in self._clusters:
276             for cluster in self._clusters:
279             max_clock_cluster = max(self._clusters,
281             self.l3 = L3(clk_domain=max_clock_cluster.clk_domain)
282             self.toL3Bus = L2XBar(width=64)
283             self.toL3Bus.master = self.l3.cpu_side
284             self.l3.mem_side = self.membus.slave
285             cluster_mem_bus = self.toL3Bus
288         for cluster in self._clusters: