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11700:7d4d424c9f17 |
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26-Oct-2016 |
Tony Gutierrez <anthony.gutierrez@amd.com> |
gpu-compute: support in-order data delivery in GM pipe
this patch adds an ordered response buffer to the GM pipeline to ensure in-order data delivery. the buffer is implemented as a stl ordered map, which sorts the request in program order by using their sequence ID. when requests return to the GM pipeline they are marked as done. only the oldest request may be serviced from the ordered buffer, and only if is marked as done.
the FIFO response buffers are kept and used in OoO delivery mode
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11693:bc1f702c25b9 |
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26-Oct-2016 |
Tony Gutierrez <anthony.gutierrez@amd.com> |
hsail, gpu-compute: remove doGm/SmReturn add completeAcc
we are removing doGmReturn from the GM pipe, and adding completeAcc() implementations for the HSAIL mem ops. the behavior in doGmReturn is dependent on HSAIL and HSAIL mem ops, however the completion phase of memory ops in machine ISA can be very different, even amongst individual machine ISA mem ops. so we remove this functionality from the pipeline and allow it to be implemented by the individual instructions.
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