atomic_stat_config.ini (10016:dffa80408656) | atomic_stat_config.ini (10354:2d6d7a056a38) |
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1# Copyright (c) 2012 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 26 unchanged lines hidden (view full) --- 35# 36# Author: Dam Sunwoo 37# 38# Sample stats config file (AtomicSimpleCPU) for m5stats2streamline.py 39# 40# Stats grouped together will show as grouped in Streamline. 41# E.g., 42# | 1# Copyright (c) 2012 ARM Limited 2# All rights reserved 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 26 unchanged lines hidden (view full) --- 35# 36# Author: Dam Sunwoo 37# 38# Sample stats config file (AtomicSimpleCPU) for m5stats2streamline.py 39# 40# Stats grouped together will show as grouped in Streamline. 41# E.g., 42# |
43# icache = 44# icache.overall_hits::total 45# icache.overall_misses::total | 43# commit_inst_count = 44# system.cluster.cpu#.commit.committedInsts 45# system.cluster.cpu#.commit.commitSquashedInsts |
46# | 46# |
47# will display the icache as a stacked line chart. | 47# will display the inst counts (committed/squashed) as a stacked line chart. |
48# Charts will still be configurable in Streamline. 49 50[PER_CPU_STATS] | 48# Charts will still be configurable in Streamline. 49 50[PER_CPU_STATS] |
51# "system.cpu#." will automatically prepended for per-CPU stats | 51# '#' will be automatically replaced with the correct CPU id. |
52 | 52 |
53commit_inst_count = 54 system.cluster.cpu#.committedInsts 55 |
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53cycles = | 56cycles = |
54 num_busy_cycles 55 num_idle_cycles | 57 system.cluster.cpu#.num_busy_cycles 58 system.cluster.cpu#.num_idle_cycles |
56 57register_access = | 59 60register_access = |
58 num_int_register_reads 59 num_int_register_writes | 61 system.cluster.cpu#.num_int_register_reads 62 system.cluster.cpu#.num_int_register_writes |
60 61mem_refs = | 63 64mem_refs = |
62 num_mem_refs | 65 system.cluster.cpu#.num_mem_refs |
63 64inst_breakdown = | 66 67inst_breakdown = |
65 num_conditional_control_insts 66 num_int_insts 67 num_fp_insts 68 num_load_insts 69 num_store_insts | 68 system.cluster.cpu#.num_conditional_control_insts 69 system.cluster.cpu#.num_int_insts 70 system.cluster.cpu#.num_fp_insts 71 system.cluster.cpu#.num_load_insts 72 system.cluster.cpu#.num_store_insts |
70 71icache = | 73 74icache = |
72 icache.overall_hits::total 73 icache.overall_misses::total | 75 system.cluster.il1_cache#.overall_hits::total 76 system.cluster.il1_cache#.overall_misses::total |
74 75dcache = | 77 78dcache = |
76 dcache.overall_hits::total 77 dcache.overall_misses::total | 79 system.cluster.dl1_cache#.overall_hits::total 80 system.cluster.dl1_cache#.overall_misses::total |
78 | 81 |
79[PER_SWITCHCPU_STATS] 80# If starting from checkpoints, gem5 keeps CPU stats in system.switch_cpus# structures. 81# List per-switchcpu stats here if any 82# "system.switch_cpus#" will automatically prepended for per-CPU stats 83 | |
84[PER_L2_STATS] | 82[PER_L2_STATS] |
83# '#' will be automatically replaced with the correct L2 id. |
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85 86l2_cache = | 84 85l2_cache = |
87 overall_hits::total 88 overall_misses::total | 86 system.cluster.l2_cache#.overall_hits::total 87 system.cluster.l2_cache#.overall_misses::total |
89 90[OTHER_STATS] | 88 89[OTHER_STATS] |
90# Anything that doesn't belong to CPU or L2 caches |
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91 92physmem = | 91 92physmem = |
93 system.physmem.bw_total::total | 93 system.memsys.mem_ctrls.bytes_read::total 94 system.memsys.mem_ctrls.bytes_written::total |