1# Copyright (c) 2012 ARM Limited
2# All rights reserved
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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35#
36# Author: Dam Sunwoo
37#
38# Sample stats config file (AtomicSimpleCPU) for m5stats2streamline.py
39#
40# Stats grouped together will show as grouped in Streamline.
41# E.g.,
42#
43# icache =
44# icache.overall_hits::total
45# icache.overall_misses::total
46#
47# will display the icache as a stacked line chart.
48# Charts will still be configurable in Streamline.
49
50[PER_CPU_STATS]
51# "system.cpu#." will automatically prepended for per-CPU stats
52
53cycles =
54 num_busy_cycles
55 num_idle_cycles
56
57register_access =
58 num_int_register_reads
59 num_int_register_writes
60
61mem_refs =
62 num_mem_refs
63
64inst_breakdown =
65 num_conditional_control_insts
66 num_int_insts
67 num_fp_insts
68 num_load_insts
69 num_store_insts
70
71icache =
72 icache.overall_hits::total
73 icache.overall_misses::total
74
75dcache =
76 dcache.overall_hits::total
77 dcache.overall_misses::total
78
79[PER_SWITCHCPU_STATS]
80# If starting from checkpoints, gem5 keeps CPU stats in system.switch_cpus# structures.
81# List per-switchcpu stats here if any
82# "system.switch_cpus#" will automatically prepended for per-CPU stats
83
84[PER_L2_STATS]
85
86l2_cache =
87 overall_hits::total
88 overall_misses::total
89
90[OTHER_STATS]
91
92physmem =
93 system.physmem.bw_total::total