m5op_alpha.S (12157:c27b548bad70) | m5op_alpha.S (12160:c282cb504275) |
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1/* 2 * Copyright (c) 2003-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 80 unchanged lines hidden (view full) --- 89#define AN_PQ INST(m5_op, M5OP_AN_PQ, 0, M5OP_ANNOTATE) 90#define AN_L INST(m5_op, M5OP_AN_L, 0, M5OP_ANNOTATE) 91#define AN_IDENTIFY INST(m5_op, M5OP_AN_IDENTIFY, 0, M5OP_ANNOTATE) 92#define AN_GETID INST(m5_op, M5OP_AN_GETID, 0, M5OP_ANNOTATE) 93 94 95 .set noreorder 96 | 1/* 2 * Copyright (c) 2003-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 80 unchanged lines hidden (view full) --- 89#define AN_PQ INST(m5_op, M5OP_AN_PQ, 0, M5OP_ANNOTATE) 90#define AN_L INST(m5_op, M5OP_AN_L, 0, M5OP_ANNOTATE) 91#define AN_IDENTIFY INST(m5_op, M5OP_AN_IDENTIFY, 0, M5OP_ANNOTATE) 92#define AN_GETID INST(m5_op, M5OP_AN_GETID, 0, M5OP_ANNOTATE) 93 94 95 .set noreorder 96 |
97SIMPLE_OP(arm, ARM(16)) 98SIMPLE_OP(quiesce, QUIESCE) 99SIMPLE_OP(quiesceNs, QUIESCENS(16)) 100SIMPLE_OP(quiesceCycle, QUIESCECYC(16)) 101SIMPLE_OP(quiesceTime, QUIESCETIME) 102SIMPLE_OP(rpns, RPNS) 103SIMPLE_OP(wakeCPU, WAKE_CPU(16)) | 97SIMPLE_OP(m5_arm, ARM(16)) 98SIMPLE_OP(m5_quiesce, QUIESCE) 99SIMPLE_OP(m5_quiesce_ns, QUIESCENS(16)) 100SIMPLE_OP(m5_quiesce_cycle, QUIESCECYC(16)) 101SIMPLE_OP(m5_quiesce_time, QUIESCETIME) 102SIMPLE_OP(m5_rpns, RPNS) 103SIMPLE_OP(m5_wake_cpu, WAKE_CPU(16)) |
104SIMPLE_OP(m5_exit, M5EXIT(16)) | 104SIMPLE_OP(m5_exit, M5EXIT(16)) |
105SIMPLE_OP(m5_initparam, INITPARAM(0)) 106SIMPLE_OP(m5_loadsymbol, LOADSYMBOL(0)) | 105SIMPLE_OP(m5_init_param, INITPARAM(0)) 106SIMPLE_OP(m5_load_symbol, LOADSYMBOL(0)) |
107SIMPLE_OP(m5_reset_stats, RESET_STATS(16, 17)) 108SIMPLE_OP(m5_dump_stats, DUMP_STATS(16, 17)) | 107SIMPLE_OP(m5_reset_stats, RESET_STATS(16, 17)) 108SIMPLE_OP(m5_dump_stats, DUMP_STATS(16, 17)) |
109SIMPLE_OP(m5_dumpreset_stats, DUMPRST_STATS(16, 17)) | 109SIMPLE_OP(m5_dump_reset_stats, DUMPRST_STATS(16, 17)) |
110SIMPLE_OP(m5_checkpoint, CHECKPOINT(16, 17)) | 110SIMPLE_OP(m5_checkpoint, CHECKPOINT(16, 17)) |
111SIMPLE_OP(m5_readfile, READFILE) 112SIMPLE_OP(m5_debugbreak, DEBUGBREAK) 113SIMPLE_OP(m5_switchcpu, SWITCHCPU) 114SIMPLE_OP(m5_addsymbol, ADDSYMBOL(16, 17)) | 111SIMPLE_OP(m5_read_file, READFILE) 112SIMPLE_OP(m5_debug_break, DEBUGBREAK) 113SIMPLE_OP(m5_switch_cpu, SWITCHCPU) 114SIMPLE_OP(m5_add_symbol, ADDSYMBOL(16, 17)) |
115SIMPLE_OP(m5_panic, PANIC) 116 117SIMPLE_OP(m5a_bsm, AN_BSM) 118SIMPLE_OP(m5a_esm, AN_ESM) 119SIMPLE_OP(m5a_begin, AN_BEGIN) 120SIMPLE_OP(m5a_end, AN_END) 121SIMPLE_OP(m5a_q, AN_Q) 122SIMPLE_OP(m5a_rq, AN_RQ) 123SIMPLE_OP(m5a_dq, AN_DQ) 124SIMPLE_OP(m5a_wf, AN_WF) 125SIMPLE_OP(m5a_we, AN_WE) 126SIMPLE_OP(m5a_ws, AN_WS) 127SIMPLE_OP(m5a_sq, AN_SQ) 128SIMPLE_OP(m5a_aq, AN_AQ) 129SIMPLE_OP(m5a_pq, AN_PQ) 130SIMPLE_OP(m5a_l, AN_L) 131SIMPLE_OP(m5a_identify, AN_IDENTIFY) 132SIMPLE_OP(m5a_getid, AN_GETID) 133 | 115SIMPLE_OP(m5_panic, PANIC) 116 117SIMPLE_OP(m5a_bsm, AN_BSM) 118SIMPLE_OP(m5a_esm, AN_ESM) 119SIMPLE_OP(m5a_begin, AN_BEGIN) 120SIMPLE_OP(m5a_end, AN_END) 121SIMPLE_OP(m5a_q, AN_Q) 122SIMPLE_OP(m5a_rq, AN_RQ) 123SIMPLE_OP(m5a_dq, AN_DQ) 124SIMPLE_OP(m5a_wf, AN_WF) 125SIMPLE_OP(m5a_we, AN_WE) 126SIMPLE_OP(m5a_ws, AN_WS) 127SIMPLE_OP(m5a_sq, AN_SQ) 128SIMPLE_OP(m5a_aq, AN_AQ) 129SIMPLE_OP(m5a_pq, AN_PQ) 130SIMPLE_OP(m5a_l, AN_L) 131SIMPLE_OP(m5a_identify, AN_IDENTIFY) 132SIMPLE_OP(m5a_getid, AN_GETID) 133 |