1/* 2 * Copyright (c) 2003-2006 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Nathan Binkert 29 * Ali Saidi 30 */ 31 32#define m5_op 0x01 33 34#include "m5ops.h" 35 36#define INST(op, ra, rb, func) \ 37 .long (((op) << 26) | ((ra) << 21) | ((rb) << 16) | (func)) 38 39#define LEAF(func) \ 40 .align 3; \ 41 .globl func; \ 42 .ent func; \ 43func: 44 45#define RET \ 46 ret ($26) 47 48#define END(func) \ 49 .end func 50
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51#define SIMPLE_OP(_f, _o) \ 52 LEAF(_f) \ 53 _o; \ 54 RET; \ 55 END(_f) 56 |
57#define ARM(reg) INST(m5_op, reg, 0, arm_func) 58#define QUIESCE INST(m5_op, 0, 0, quiesce_func) 59#define QUIESCENS(r1) INST(m5_op, r1, 0, quiescens_func) 60#define QUIESCECYC(r1) INST(m5_op, r1, 0, quiescecycle_func) 61#define QUIESCETIME INST(m5_op, 0, 0, quiescetime_func) 62#define M5EXIT(reg) INST(m5_op, reg, 0, exit_func) 63#define INITPARAM(reg) INST(m5_op, reg, 0, initparam_func) 64#define LOADSYMBOL(reg) INST(m5_op, reg, 0, loadsymbol_func) 65#define RESET_STATS(r1, r2) INST(m5_op, r1, r2, resetstats_func) 66#define DUMP_STATS(r1, r2) INST(m5_op, r1, r2, dumpstats_func) 67#define DUMPRST_STATS(r1, r2) INST(m5_op, r1, r2, dumprststats_func) 68#define CHECKPOINT(r1, r2) INST(m5_op, r1, r2, ckpt_func) 69#define READFILE INST(m5_op, 0, 0, readfile_func) 70#define DEBUGBREAK INST(m5_op, 0, 0, debugbreak_func) 71#define SWITCHCPU INST(m5_op, 0, 0, switchcpu_func) 72#define ADDSYMBOL(r1,r2) INST(m5_op, r1, r2, addsymbol_func) 73#define PANIC INST(m5_op, 0, 0, panic_func)
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68#define AN_BEGIN(r1) INST(m5_op, r1, 0, anbegin_func)
69#define AN_WAIT(r1,r2) INST(m5_op, r1, r2, anwait_func)
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74 75 .set noreorder 76
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73 .align 4
74LEAF(arm)
75 ARM(16)
76 RET
77END(arm)
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77SIMPLE_OP(arm, ARM(16)) 78SIMPLE_OP(quiesce, QUIESCE) 79SIMPLE_OP(quiesceNs, QUIESCENS(16)) 80SIMPLE_OP(quiesceCycle, QUIESCECYC(16)) 81SIMPLE_OP(quiesceTime, QUIESCETIME) 82SIMPLE_OP(m5_exit, M5EXIT(16)) 83SIMPLE_OP(m5_initparam, INITPARAM(0)) 84SIMPLE_OP(m5_loadsymbol, LOADSYMBOL(0)) 85SIMPLE_OP(m5_reset_stats, RESET_STATS(16, 17)) 86SIMPLE_OP(m5_dump_stats, DUMP_STATS(16, 17)) 87SIMPLE_OP(m5_dumpreset_stats, DUMPRST_STATS(16, 17)) 88SIMPLE_OP(m5_checkpoint, CHECKPOINT(16, 17)) 89SIMPLE_OP(m5_readfile, READFILE) 90SIMPLE_OP(m5_debugbreak, DEBUGBREAK) 91SIMPLE_OP(m5_switchcpu, SWITCHCPU) 92SIMPLE_OP(m5_addsymbol, ADDSYMBOL(16, 17)) 93SIMPLE_OP(m5_panic, PANIC) |
94
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79 .align 4
80LEAF(quiesce)
81 QUIESCE
82 RET
83END(quiesce)
84
85 .align 4
86LEAF(quiesceNs)
87 QUIESCENS(16)
88 RET
89END(quiesceNs)
90
91 .align 4
92LEAF(quiesceCycle)
93 QUIESCECYC(16)
94 RET
95END(quiesceCycle)
96
97 .align 4
98LEAF(quiesceTime)
99 QUIESCETIME
100 RET
101END(quiesceTime)
102
103 .align 4
104LEAF(m5_exit)
105 M5EXIT(16)
106 RET
107END(m5_exit)
108
109 .align 4
110LEAF(m5_initparam)
111 INITPARAM(0)
112 RET
113END(m5_initparam)
114
115 .align 4
116LEAF(m5_loadsymbol)
117 LOADSYMBOL(0)
118 RET
119END(m5_loadsymbol)
120
121 .align 4
122LEAF(m5_reset_stats)
123 RESET_STATS(16, 17)
124 RET
125END(m5_reset_stats)
126
127 .align 4
128LEAF(m5_dump_stats)
129 DUMP_STATS(16, 17)
130 RET
131END(m5_dump_stats)
132
133 .align 4
134LEAF(m5_dumpreset_stats)
135 DUMPRST_STATS(16, 17)
136 RET
137END(m5_dumpreset_stats)
138
139 .align 4
140LEAF(m5_checkpoint)
141 CHECKPOINT(16, 17)
142 RET
143END(m5_checkpoint)
144
145 .align 4
146LEAF(m5_readfile)
147 READFILE
148 RET
149END(m5_readfile)
150
151 .align 4
152LEAF(m5_debugbreak)
153 DEBUGBREAK
154 RET
155END(m5_debugbreak)
156
157 .align 4
158LEAF(m5_switchcpu)
159 SWITCHCPU
160 RET
161END(m5_switchcpu)
162
163 .align 4
164LEAF(m5_addsymbol)
165 ADDSYMBOL(16, 17)
166 RET
167END(m5_addsymbol)
168
169 .align 4
170LEAF(m5_panic)
171 PANIC
172 RET
173END(m5_panic)
174
175
176 .align 4
177LEAF(m5_anbegin)
178 AN_BEGIN(16)
179 RET
180END(m5_anbegin)
181
182
183 .align 4
184LEAF(m5_anwait)
185 AN_WAIT(16,17)
186 RET
187END(m5_anwait)
188
189
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