1/*
2 * Copyright (c) 2003-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 * Ali Saidi
30 */
31
32#define m5_op 0x01
33
34#include "m5ops.h"
35
36#define INST(op, ra, rb, func) \
37 .long (((op) << 26) | ((ra) << 21) | ((rb) << 16) | (func))
38
39#define LEAF(func) \
40 .align 3; \
41 .globl func; \
42 .ent func; \
43func:
44
45#define RET \
46 ret ($26)
47
48#define END(func) \
49 .end func
50
51#define SIMPLE_OP(_f, _o) \
52 LEAF(_f) \
53 _o; \
54 RET; \
55 END(_f)
56
57#define ARM(reg) INST(m5_op, reg, 0, arm_func)
58#define QUIESCE INST(m5_op, 0, 0, quiesce_func)
59#define QUIESCENS(r1) INST(m5_op, r1, 0, quiescens_func)
60#define QUIESCECYC(r1) INST(m5_op, r1, 0, quiescecycle_func)
61#define QUIESCETIME INST(m5_op, 0, 0, quiescetime_func)
| 1/*
2 * Copyright (c) 2003-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 * Ali Saidi
30 */
31
32#define m5_op 0x01
33
34#include "m5ops.h"
35
36#define INST(op, ra, rb, func) \
37 .long (((op) << 26) | ((ra) << 21) | ((rb) << 16) | (func))
38
39#define LEAF(func) \
40 .align 3; \
41 .globl func; \
42 .ent func; \
43func:
44
45#define RET \
46 ret ($26)
47
48#define END(func) \
49 .end func
50
51#define SIMPLE_OP(_f, _o) \
52 LEAF(_f) \
53 _o; \
54 RET; \
55 END(_f)
56
57#define ARM(reg) INST(m5_op, reg, 0, arm_func)
58#define QUIESCE INST(m5_op, 0, 0, quiesce_func)
59#define QUIESCENS(r1) INST(m5_op, r1, 0, quiescens_func)
60#define QUIESCECYC(r1) INST(m5_op, r1, 0, quiescecycle_func)
61#define QUIESCETIME INST(m5_op, 0, 0, quiescetime_func)
|
| 62#define RPNS INST(m5_op, 0, 0, rpns_func)
|
62#define M5EXIT(reg) INST(m5_op, reg, 0, exit_func)
63#define INITPARAM(reg) INST(m5_op, reg, 0, initparam_func)
64#define LOADSYMBOL(reg) INST(m5_op, reg, 0, loadsymbol_func)
65#define RESET_STATS(r1, r2) INST(m5_op, r1, r2, resetstats_func)
66#define DUMP_STATS(r1, r2) INST(m5_op, r1, r2, dumpstats_func)
67#define DUMPRST_STATS(r1, r2) INST(m5_op, r1, r2, dumprststats_func)
68#define CHECKPOINT(r1, r2) INST(m5_op, r1, r2, ckpt_func)
69#define READFILE INST(m5_op, 0, 0, readfile_func)
70#define DEBUGBREAK INST(m5_op, 0, 0, debugbreak_func)
71#define SWITCHCPU INST(m5_op, 0, 0, switchcpu_func)
72#define ADDSYMBOL(r1,r2) INST(m5_op, r1, r2, addsymbol_func)
73#define PANIC INST(m5_op, 0, 0, panic_func)
74
75 .set noreorder
76
77SIMPLE_OP(arm, ARM(16))
78SIMPLE_OP(quiesce, QUIESCE)
79SIMPLE_OP(quiesceNs, QUIESCENS(16))
80SIMPLE_OP(quiesceCycle, QUIESCECYC(16))
81SIMPLE_OP(quiesceTime, QUIESCETIME)
| 63#define M5EXIT(reg) INST(m5_op, reg, 0, exit_func)
64#define INITPARAM(reg) INST(m5_op, reg, 0, initparam_func)
65#define LOADSYMBOL(reg) INST(m5_op, reg, 0, loadsymbol_func)
66#define RESET_STATS(r1, r2) INST(m5_op, r1, r2, resetstats_func)
67#define DUMP_STATS(r1, r2) INST(m5_op, r1, r2, dumpstats_func)
68#define DUMPRST_STATS(r1, r2) INST(m5_op, r1, r2, dumprststats_func)
69#define CHECKPOINT(r1, r2) INST(m5_op, r1, r2, ckpt_func)
70#define READFILE INST(m5_op, 0, 0, readfile_func)
71#define DEBUGBREAK INST(m5_op, 0, 0, debugbreak_func)
72#define SWITCHCPU INST(m5_op, 0, 0, switchcpu_func)
73#define ADDSYMBOL(r1,r2) INST(m5_op, r1, r2, addsymbol_func)
74#define PANIC INST(m5_op, 0, 0, panic_func)
75
76 .set noreorder
77
78SIMPLE_OP(arm, ARM(16))
79SIMPLE_OP(quiesce, QUIESCE)
80SIMPLE_OP(quiesceNs, QUIESCENS(16))
81SIMPLE_OP(quiesceCycle, QUIESCECYC(16))
82SIMPLE_OP(quiesceTime, QUIESCETIME)
|
| 83SIMPLE_OP(rpns, RPNS)
|
82SIMPLE_OP(m5_exit, M5EXIT(16))
83SIMPLE_OP(m5_initparam, INITPARAM(0))
84SIMPLE_OP(m5_loadsymbol, LOADSYMBOL(0))
85SIMPLE_OP(m5_reset_stats, RESET_STATS(16, 17))
86SIMPLE_OP(m5_dump_stats, DUMP_STATS(16, 17))
87SIMPLE_OP(m5_dumpreset_stats, DUMPRST_STATS(16, 17))
88SIMPLE_OP(m5_checkpoint, CHECKPOINT(16, 17))
89SIMPLE_OP(m5_readfile, READFILE)
90SIMPLE_OP(m5_debugbreak, DEBUGBREAK)
91SIMPLE_OP(m5_switchcpu, SWITCHCPU)
92SIMPLE_OP(m5_addsymbol, ADDSYMBOL(16, 17))
93SIMPLE_OP(m5_panic, PANIC)
94
| 84SIMPLE_OP(m5_exit, M5EXIT(16))
85SIMPLE_OP(m5_initparam, INITPARAM(0))
86SIMPLE_OP(m5_loadsymbol, LOADSYMBOL(0))
87SIMPLE_OP(m5_reset_stats, RESET_STATS(16, 17))
88SIMPLE_OP(m5_dump_stats, DUMP_STATS(16, 17))
89SIMPLE_OP(m5_dumpreset_stats, DUMPRST_STATS(16, 17))
90SIMPLE_OP(m5_checkpoint, CHECKPOINT(16, 17))
91SIMPLE_OP(m5_readfile, READFILE)
92SIMPLE_OP(m5_debugbreak, DEBUGBREAK)
93SIMPLE_OP(m5_switchcpu, SWITCHCPU)
94SIMPLE_OP(m5_addsymbol, ADDSYMBOL(16, 17))
95SIMPLE_OP(m5_panic, PANIC)
96
|