| stats.txt (11687:b3d5f0e9e258) | stats.txt (11955:1170d039b31e) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.230201 # Number of seconds simulated 4sim_ticks 230201146500 # Number of ticks simulated 5final_tick 230201146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1601768 # Simulator instruction rate (inst/s) 8host_op_rate 1688668 # Simulator op (including micro ops) rate (op/s) --- 138 unchanged lines hidden (view full) --- 147system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 148system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 149system.cpu.itb.read_accesses 0 # DTB read accesses 150system.cpu.itb.write_accesses 0 # DTB write accesses 151system.cpu.itb.inst_accesses 0 # ITB inst accesses 152system.cpu.itb.hits 0 # DTB hits 153system.cpu.itb.misses 0 # DTB misses 154system.cpu.itb.accesses 0 # DTB accesses | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.230201 # Number of seconds simulated 4sim_ticks 230201146500 # Number of ticks simulated 5final_tick 230201146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 1601768 # Simulator instruction rate (inst/s) 8host_op_rate 1688668 # Simulator op (including micro ops) rate (op/s) --- 138 unchanged lines hidden (view full) --- 147system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 148system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 149system.cpu.itb.read_accesses 0 # DTB read accesses 150system.cpu.itb.write_accesses 0 # DTB write accesses 151system.cpu.itb.inst_accesses 0 # ITB inst accesses 152system.cpu.itb.hits 0 # DTB hits 153system.cpu.itb.misses 0 # DTB misses 154system.cpu.itb.accesses 0 # DTB accesses |
| 155system.cpu.workload.num_syscalls 400 # Number of system calls | 155system.cpu.workload.numSyscalls 400 # Number of system calls |
| 156system.cpu.pwrStateResidencyTicks::ON 230201146500 # Cumulative time (in ticks) in various power states 157system.cpu.numCycles 460402293 # number of cpu cycles simulated 158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 160system.cpu.committedInsts 171842484 # Number of instructions committed 161system.cpu.committedOps 181165371 # Number of ops (including micro ops) committed 162system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses 163system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses --- 506 unchanged lines hidden --- | 156system.cpu.pwrStateResidencyTicks::ON 230201146500 # Cumulative time (in ticks) in various power states 157system.cpu.numCycles 460402293 # number of cpu cycles simulated 158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 160system.cpu.committedInsts 171842484 # Number of instructions committed 161system.cpu.committedOps 181165371 # Number of ops (including micro ops) committed 162system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses 163system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses --- 506 unchanged lines hidden --- |