Cross Reference: /gem5/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 0.230198 # Number of seconds simulated
4sim_ticks 230197694500 # Number of ticks simulated
5final_tick 230197694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 0.230201 # Number of seconds simulated
4sim_ticks 230201146500 # Number of ticks simulated
5final_tick 230201146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 688414 # Simulator instruction rate (inst/s)
8host_op_rate 725763 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 922189750 # Simulator tick rate (ticks/s)
10host_mem_usage 268612 # Number of bytes of host memory used
11host_seconds 249.62 # Real time elapsed on the host

7host_inst_rate 826360 # Simulator instruction rate (inst/s)
8host_op_rate 871192 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1106995865 # Simulator tick rate (ticks/s)
10host_mem_usage 273252 # Number of bytes of host memory used
11host_seconds 207.95 # Real time elapsed on the host

12sim_insts 171842484 # Number of instructions simulated
13sim_ops 181165371 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states

16system.physmem.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states

17system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory
19system.physmem.bytes_read::total 220992 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 110656 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 110656 # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory
24system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory

25system.physmem.bw_read::cpu.inst 480700 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::cpu.data 479310 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 960010 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 480700 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 480700 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_total::cpu.inst 480700 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::cpu.data 479310 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bw_total::total 960010 # Total bandwidth to/from this memory (bytes/s)
33system.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states

25system.physmem.bw_read::cpu.inst 480693 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::cpu.data 479303 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 959995 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 480693 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 480693 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_total::cpu.inst 480693 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::cpu.data 479303 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bw_total::total 959995 # Total bandwidth to/from this memory (bytes/s)
33system.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states

34system.cpu_clk_domain.clock 500 # Clock period in ticks

35system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states

35system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states

36system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

57system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
58system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
59system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
60system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
61system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
62system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
63system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
64system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

65system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states

65system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states

66system.cpu.dtb.walker.walks 0 # Table walker walks requested
67system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
68system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
69system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
70system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
71system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
72system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
73system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

87system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
88system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
89system.cpu.dtb.read_accesses 0 # DTB read accesses
90system.cpu.dtb.write_accesses 0 # DTB write accesses
91system.cpu.dtb.inst_accesses 0 # ITB inst accesses
92system.cpu.dtb.hits 0 # DTB hits
93system.cpu.dtb.misses 0 # DTB misses
94system.cpu.dtb.accesses 0 # DTB accesses

95system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states

95system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states

96system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

117system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
118system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
119system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
120system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
121system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
122system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
123system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
124system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

125system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states

125system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states

126system.cpu.itb.walker.walks 0 # Table walker walks requested
127system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
128system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
129system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
130system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
131system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
132system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
133system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

148system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
149system.cpu.itb.read_accesses 0 # DTB read accesses
150system.cpu.itb.write_accesses 0 # DTB write accesses
151system.cpu.itb.inst_accesses 0 # ITB inst accesses
152system.cpu.itb.hits 0 # DTB hits
153system.cpu.itb.misses 0 # DTB misses
154system.cpu.itb.accesses 0 # DTB accesses
155system.cpu.workload.num_syscalls 400 # Number of system calls

156system.cpu.pwrStateResidencyTicks::ON 230197694500 # Cumulative time (in ticks) in various power states
157system.cpu.numCycles 460395389 # number of cpu cycles simulated

156system.cpu.pwrStateResidencyTicks::ON 230201146500 # Cumulative time (in ticks) in various power states
157system.cpu.numCycles 460402293 # number of cpu cycles simulated

158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
160system.cpu.committedInsts 171842484 # Number of instructions committed
161system.cpu.committedOps 181165371 # Number of ops (including micro ops) committed
162system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses
163system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
164system.cpu.num_func_calls 3545028 # number of times a function call or return occured
165system.cpu.num_conditional_control_insts 32201008 # number of instructions that are conditional controls

--- 4 unchanged lines hidden (view full) ---

170system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read
171system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written
172system.cpu.num_cc_register_reads 626384530 # number of times the CC registers were read
173system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written
174system.cpu.num_mem_refs 40540779 # number of memory refs
175system.cpu.num_load_insts 27896144 # Number of load instructions
176system.cpu.num_store_insts 12644635 # Number of store instructions
177system.cpu.num_idle_cycles 0.002000 # Number of idle cycles

178system.cpu.num_busy_cycles 460395388.998000 # Number of busy cycles

178system.cpu.num_busy_cycles 460402292.998000 # Number of busy cycles

179system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
180system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
181system.cpu.Branches 40300312 # Number of branches fetched
182system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
183system.cpu.op_class::IntAlu 138988213 76.51% 76.51% # Class of executed instruction
184system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction
185system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction
186system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction

--- 22 unchanged lines hidden (view full) ---

209system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction
210system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction
211system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction
212system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction
213system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction
214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
216system.cpu.op_class::total 181650743 # Class of executed instruction

217system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states

217system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states

218system.cpu.dcache.tags.replacements 40 # number of replacements

219system.cpu.dcache.tags.tagsinuse 1363.571253 # Cycle average of tags in use

219system.cpu.dcache.tags.tagsinuse 1363.564425 # Cycle average of tags in use

220system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks.
221system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks.
222system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks.
223system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

224system.cpu.dcache.tags.occ_blocks::cpu.data 1363.571253 # Average occupied blocks per requestor
225system.cpu.dcache.tags.occ_percent::cpu.data 0.332903 # Average percentage of cache occupancy
226system.cpu.dcache.tags.occ_percent::total 0.332903 # Average percentage of cache occupancy

224system.cpu.dcache.tags.occ_blocks::cpu.data 1363.564425 # Average occupied blocks per requestor
225system.cpu.dcache.tags.occ_percent::cpu.data 0.332901 # Average percentage of cache occupancy
226system.cpu.dcache.tags.occ_percent::total 0.332901 # Average percentage of cache occupancy

227system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id
228system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id
229system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
230system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
231system.cpu.dcache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id
232system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 # Occupied blocks per task id
233system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 # Percentage of cache occupancy per task id
234system.cpu.dcache.tags.tag_accesses 80330619 # Number of tag accesses
235system.cpu.dcache.tags.data_accesses 80330619 # Number of data accesses

236system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states

236system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states

237system.cpu.dcache.ReadReq_hits::cpu.data 27754163 # number of ReadReq hits
238system.cpu.dcache.ReadReq_hits::total 27754163 # number of ReadReq hits
239system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits
240system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits
241system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits
242system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits
243system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits
244system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits

--- 8 unchanged lines hidden (view full) ---

253system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses
254system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses
255system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
256system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
257system.cpu.dcache.demand_misses::cpu.data 1788 # number of demand (read+write) misses
258system.cpu.dcache.demand_misses::total 1788 # number of demand (read+write) misses
259system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses
260system.cpu.dcache.overall_misses::total 1789 # number of overall misses

261system.cpu.dcache.ReadReq_miss_latency::cpu.data 39940000 # number of ReadReq miss cycles
262system.cpu.dcache.ReadReq_miss_latency::total 39940000 # number of ReadReq miss cycles
263system.cpu.dcache.WriteReq_miss_latency::cpu.data 67838500 # number of WriteReq miss cycles
264system.cpu.dcache.WriteReq_miss_latency::total 67838500 # number of WriteReq miss cycles
265system.cpu.dcache.demand_miss_latency::cpu.data 107778500 # number of demand (read+write) miss cycles
266system.cpu.dcache.demand_miss_latency::total 107778500 # number of demand (read+write) miss cycles
267system.cpu.dcache.overall_miss_latency::cpu.data 107778500 # number of overall miss cycles
268system.cpu.dcache.overall_miss_latency::total 107778500 # number of overall miss cycles

261system.cpu.dcache.ReadReq_miss_latency::cpu.data 40571000 # number of ReadReq miss cycles
262system.cpu.dcache.ReadReq_miss_latency::total 40571000 # number of ReadReq miss cycles
263system.cpu.dcache.WriteReq_miss_latency::cpu.data 68930500 # number of WriteReq miss cycles
264system.cpu.dcache.WriteReq_miss_latency::total 68930500 # number of WriteReq miss cycles
265system.cpu.dcache.demand_miss_latency::cpu.data 109501500 # number of demand (read+write) miss cycles
266system.cpu.dcache.demand_miss_latency::total 109501500 # number of demand (read+write) miss cycles
267system.cpu.dcache.overall_miss_latency::cpu.data 109501500 # number of overall miss cycles
268system.cpu.dcache.overall_miss_latency::total 109501500 # number of overall miss cycles

269system.cpu.dcache.ReadReq_accesses::cpu.data 27754851 # number of ReadReq accesses(hits+misses)
270system.cpu.dcache.ReadReq_accesses::total 27754851 # number of ReadReq accesses(hits+misses)
271system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
272system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
273system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses)
274system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses)
275system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
276system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)

--- 8 unchanged lines hidden (view full) ---

285system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses
286system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses
287system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses
288system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses
289system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 # miss rate for demand accesses
290system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
291system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses
292system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses

293system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58052.325581 # average ReadReq miss latency
294system.cpu.dcache.ReadReq_avg_miss_latency::total 58052.325581 # average ReadReq miss latency
295system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61671.363636 # average WriteReq miss latency
296system.cpu.dcache.WriteReq_avg_miss_latency::total 61671.363636 # average WriteReq miss latency
297system.cpu.dcache.demand_avg_miss_latency::cpu.data 60278.803132 # average overall miss latency
298system.cpu.dcache.demand_avg_miss_latency::total 60278.803132 # average overall miss latency
299system.cpu.dcache.overall_avg_miss_latency::cpu.data 60245.108999 # average overall miss latency
300system.cpu.dcache.overall_avg_miss_latency::total 60245.108999 # average overall miss latency

293system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58969.476744 # average ReadReq miss latency
294system.cpu.dcache.ReadReq_avg_miss_latency::total 58969.476744 # average ReadReq miss latency
295system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62664.090909 # average WriteReq miss latency
296system.cpu.dcache.WriteReq_avg_miss_latency::total 62664.090909 # average WriteReq miss latency
297system.cpu.dcache.demand_avg_miss_latency::cpu.data 61242.449664 # average overall miss latency
298system.cpu.dcache.demand_avg_miss_latency::total 61242.449664 # average overall miss latency
299system.cpu.dcache.overall_avg_miss_latency::cpu.data 61208.216881 # average overall miss latency
300system.cpu.dcache.overall_avg_miss_latency::total 61208.216881 # average overall miss latency

301system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
302system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
303system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
304system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
305system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
306system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
307system.cpu.dcache.writebacks::writebacks 16 # number of writebacks
308system.cpu.dcache.writebacks::total 16 # number of writebacks
309system.cpu.dcache.ReadReq_mshr_misses::cpu.data 688 # number of ReadReq MSHR misses
310system.cpu.dcache.ReadReq_mshr_misses::total 688 # number of ReadReq MSHR misses
311system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses
312system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses
313system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
314system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
315system.cpu.dcache.demand_mshr_misses::cpu.data 1788 # number of demand (read+write) MSHR misses
316system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses
317system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses
318system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses

319system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39252000 # number of ReadReq MSHR miss cycles
320system.cpu.dcache.ReadReq_mshr_miss_latency::total 39252000 # number of ReadReq MSHR miss cycles
321system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 66738500 # number of WriteReq MSHR miss cycles
322system.cpu.dcache.WriteReq_mshr_miss_latency::total 66738500 # number of WriteReq MSHR miss cycles
323system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles
324system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles
325system.cpu.dcache.demand_mshr_miss_latency::cpu.data 105990500 # number of demand (read+write) MSHR miss cycles
326system.cpu.dcache.demand_mshr_miss_latency::total 105990500 # number of demand (read+write) MSHR miss cycles
327system.cpu.dcache.overall_mshr_miss_latency::cpu.data 106051500 # number of overall MSHR miss cycles
328system.cpu.dcache.overall_mshr_miss_latency::total 106051500 # number of overall MSHR miss cycles

319system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39883000 # number of ReadReq MSHR miss cycles
320system.cpu.dcache.ReadReq_mshr_miss_latency::total 39883000 # number of ReadReq MSHR miss cycles
321system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67830500 # number of WriteReq MSHR miss cycles
322system.cpu.dcache.WriteReq_mshr_miss_latency::total 67830500 # number of WriteReq MSHR miss cycles
323system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles
324system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles
325system.cpu.dcache.demand_mshr_miss_latency::cpu.data 107713500 # number of demand (read+write) MSHR miss cycles
326system.cpu.dcache.demand_mshr_miss_latency::total 107713500 # number of demand (read+write) MSHR miss cycles
327system.cpu.dcache.overall_mshr_miss_latency::cpu.data 107775500 # number of overall MSHR miss cycles
328system.cpu.dcache.overall_mshr_miss_latency::total 107775500 # number of overall MSHR miss cycles

329system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses
330system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
331system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
332system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses
333system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses
334system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses
335system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for demand accesses
336system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
337system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses
338system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses

339system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57052.325581 # average ReadReq mshr miss latency
340system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57052.325581 # average ReadReq mshr miss latency
341system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60671.363636 # average WriteReq mshr miss latency
342system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60671.363636 # average WriteReq mshr miss latency
343system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
344system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
345system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59278.803132 # average overall mshr miss latency
346system.cpu.dcache.demand_avg_mshr_miss_latency::total 59278.803132 # average overall mshr miss latency
347system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59279.765232 # average overall mshr miss latency
348system.cpu.dcache.overall_avg_mshr_miss_latency::total 59279.765232 # average overall mshr miss latency
349system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states

339system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57969.476744 # average ReadReq mshr miss latency
340system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57969.476744 # average ReadReq mshr miss latency
341system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61664.090909 # average WriteReq mshr miss latency
342system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61664.090909 # average WriteReq mshr miss latency
343system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency
344system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency
345system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60242.449664 # average overall mshr miss latency
346system.cpu.dcache.demand_avg_mshr_miss_latency::total 60242.449664 # average overall mshr miss latency
347system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60243.432085 # average overall mshr miss latency
348system.cpu.dcache.overall_avg_mshr_miss_latency::total 60243.432085 # average overall mshr miss latency
349system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states

350system.cpu.icache.tags.replacements 1506 # number of replacements

351system.cpu.icache.tags.tagsinuse 1147.958164 # Cycle average of tags in use

351system.cpu.icache.tags.tagsinuse 1147.953271 # Cycle average of tags in use

352system.cpu.icache.tags.total_refs 189857002 # Total number of references to valid blocks.
353system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks.
354system.cpu.icache.tags.avg_refs 62227.794821 # Average number of references to valid blocks.
355system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

356system.cpu.icache.tags.occ_blocks::cpu.inst 1147.958164 # Average occupied blocks per requestor
357system.cpu.icache.tags.occ_percent::cpu.inst 0.560526 # Average percentage of cache occupancy
358system.cpu.icache.tags.occ_percent::total 0.560526 # Average percentage of cache occupancy

356system.cpu.icache.tags.occ_blocks::cpu.inst 1147.953271 # Average occupied blocks per requestor
357system.cpu.icache.tags.occ_percent::cpu.inst 0.560524 # Average percentage of cache occupancy
358system.cpu.icache.tags.occ_percent::total 0.560524 # Average percentage of cache occupancy

359system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id
360system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
361system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
362system.cpu.icache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id
363system.cpu.icache.tags.age_task_id_blocks_1024::3 270 # Occupied blocks per task id
364system.cpu.icache.tags.age_task_id_blocks_1024::4 942 # Occupied blocks per task id
365system.cpu.icache.tags.occ_task_id_percent::1024 0.754395 # Percentage of cache occupancy per task id
366system.cpu.icache.tags.tag_accesses 379723157 # Number of tag accesses
367system.cpu.icache.tags.data_accesses 379723157 # Number of data accesses

368system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states

368system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states

369system.cpu.icache.ReadReq_hits::cpu.inst 189857002 # number of ReadReq hits
370system.cpu.icache.ReadReq_hits::total 189857002 # number of ReadReq hits
371system.cpu.icache.demand_hits::cpu.inst 189857002 # number of demand (read+write) hits
372system.cpu.icache.demand_hits::total 189857002 # number of demand (read+write) hits
373system.cpu.icache.overall_hits::cpu.inst 189857002 # number of overall hits
374system.cpu.icache.overall_hits::total 189857002 # number of overall hits
375system.cpu.icache.ReadReq_misses::cpu.inst 3051 # number of ReadReq misses
376system.cpu.icache.ReadReq_misses::total 3051 # number of ReadReq misses
377system.cpu.icache.demand_misses::cpu.inst 3051 # number of demand (read+write) misses
378system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses
379system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses
380system.cpu.icache.overall_misses::total 3051 # number of overall misses

381system.cpu.icache.ReadReq_miss_latency::cpu.inst 124592000 # number of ReadReq miss cycles
382system.cpu.icache.ReadReq_miss_latency::total 124592000 # number of ReadReq miss cycles
383system.cpu.icache.demand_miss_latency::cpu.inst 124592000 # number of demand (read+write) miss cycles
384system.cpu.icache.demand_miss_latency::total 124592000 # number of demand (read+write) miss cycles
385system.cpu.icache.overall_miss_latency::cpu.inst 124592000 # number of overall miss cycles
386system.cpu.icache.overall_miss_latency::total 124592000 # number of overall miss cycles

381system.cpu.icache.ReadReq_miss_latency::cpu.inst 126321000 # number of ReadReq miss cycles
382system.cpu.icache.ReadReq_miss_latency::total 126321000 # number of ReadReq miss cycles
383system.cpu.icache.demand_miss_latency::cpu.inst 126321000 # number of demand (read+write) miss cycles
384system.cpu.icache.demand_miss_latency::total 126321000 # number of demand (read+write) miss cycles
385system.cpu.icache.overall_miss_latency::cpu.inst 126321000 # number of overall miss cycles
386system.cpu.icache.overall_miss_latency::total 126321000 # number of overall miss cycles

387system.cpu.icache.ReadReq_accesses::cpu.inst 189860053 # number of ReadReq accesses(hits+misses)
388system.cpu.icache.ReadReq_accesses::total 189860053 # number of ReadReq accesses(hits+misses)
389system.cpu.icache.demand_accesses::cpu.inst 189860053 # number of demand (read+write) accesses
390system.cpu.icache.demand_accesses::total 189860053 # number of demand (read+write) accesses
391system.cpu.icache.overall_accesses::cpu.inst 189860053 # number of overall (read+write) accesses
392system.cpu.icache.overall_accesses::total 189860053 # number of overall (read+write) accesses
393system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses
394system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses
395system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses
396system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses
397system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
398system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses

399system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40836.447067 # average ReadReq miss latency
400system.cpu.icache.ReadReq_avg_miss_latency::total 40836.447067 # average ReadReq miss latency
401system.cpu.icache.demand_avg_miss_latency::cpu.inst 40836.447067 # average overall miss latency
402system.cpu.icache.demand_avg_miss_latency::total 40836.447067 # average overall miss latency
403system.cpu.icache.overall_avg_miss_latency::cpu.inst 40836.447067 # average overall miss latency
404system.cpu.icache.overall_avg_miss_latency::total 40836.447067 # average overall miss latency

399system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41403.146509 # average ReadReq miss latency
400system.cpu.icache.ReadReq_avg_miss_latency::total 41403.146509 # average ReadReq miss latency
401system.cpu.icache.demand_avg_miss_latency::cpu.inst 41403.146509 # average overall miss latency
402system.cpu.icache.demand_avg_miss_latency::total 41403.146509 # average overall miss latency
403system.cpu.icache.overall_avg_miss_latency::cpu.inst 41403.146509 # average overall miss latency
404system.cpu.icache.overall_avg_miss_latency::total 41403.146509 # average overall miss latency

405system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
406system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
407system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
408system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
409system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
410system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
411system.cpu.icache.writebacks::writebacks 1506 # number of writebacks
412system.cpu.icache.writebacks::total 1506 # number of writebacks
413system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3051 # number of ReadReq MSHR misses
414system.cpu.icache.ReadReq_mshr_misses::total 3051 # number of ReadReq MSHR misses
415system.cpu.icache.demand_mshr_misses::cpu.inst 3051 # number of demand (read+write) MSHR misses
416system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses
417system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses
418system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses

419system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 121541000 # number of ReadReq MSHR miss cycles
420system.cpu.icache.ReadReq_mshr_miss_latency::total 121541000 # number of ReadReq MSHR miss cycles
421system.cpu.icache.demand_mshr_miss_latency::cpu.inst 121541000 # number of demand (read+write) MSHR miss cycles
422system.cpu.icache.demand_mshr_miss_latency::total 121541000 # number of demand (read+write) MSHR miss cycles
423system.cpu.icache.overall_mshr_miss_latency::cpu.inst 121541000 # number of overall MSHR miss cycles
424system.cpu.icache.overall_mshr_miss_latency::total 121541000 # number of overall MSHR miss cycles

419system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 123270000 # number of ReadReq MSHR miss cycles
420system.cpu.icache.ReadReq_mshr_miss_latency::total 123270000 # number of ReadReq MSHR miss cycles
421system.cpu.icache.demand_mshr_miss_latency::cpu.inst 123270000 # number of demand (read+write) MSHR miss cycles
422system.cpu.icache.demand_mshr_miss_latency::total 123270000 # number of demand (read+write) MSHR miss cycles
423system.cpu.icache.overall_mshr_miss_latency::cpu.inst 123270000 # number of overall MSHR miss cycles
424system.cpu.icache.overall_mshr_miss_latency::total 123270000 # number of overall MSHR miss cycles

425system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses
426system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses
427system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses
428system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses
429system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses
430system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses

431system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39836.447067 # average ReadReq mshr miss latency
432system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39836.447067 # average ReadReq mshr miss latency
433system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency
434system.cpu.icache.demand_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency
435system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency
436system.cpu.icache.overall_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency
437system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states

431system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40403.146509 # average ReadReq mshr miss latency
432system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40403.146509 # average ReadReq mshr miss latency
433system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40403.146509 # average overall mshr miss latency
434system.cpu.icache.demand_avg_mshr_miss_latency::total 40403.146509 # average overall mshr miss latency
435system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40403.146509 # average overall mshr miss latency
436system.cpu.icache.overall_avg_mshr_miss_latency::total 40403.146509 # average overall mshr miss latency
437system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states

438system.cpu.l2cache.tags.replacements 0 # number of replacements

439system.cpu.l2cache.tags.tagsinuse 1675.610098 # Cycle average of tags in use
440system.cpu.l2cache.tags.total_refs 2846 # Total number of references to valid blocks.
441system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks.
442system.cpu.l2cache.tags.avg_refs 1.201351 # Average number of references to valid blocks.

439system.cpu.l2cache.tags.tagsinuse 2511.620011 # Cycle average of tags in use
440system.cpu.l2cache.tags.total_refs 2869 # Total number of references to valid blocks.
441system.cpu.l2cache.tags.sampled_refs 3453 # Sample count of references to valid blocks.
442system.cpu.l2cache.tags.avg_refs 0.830872 # Average number of references to valid blocks.

443system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

444system.cpu.l2cache.tags.occ_blocks::writebacks 3.037805 # Average occupied blocks per requestor
445system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.001518 # Average occupied blocks per requestor
446system.cpu.l2cache.tags.occ_blocks::cpu.data 503.570775 # Average occupied blocks per requestor
447system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy

444system.cpu.l2cache.tags.occ_blocks::cpu.inst 1168.996513 # Average occupied blocks per requestor
445system.cpu.l2cache.tags.occ_blocks::cpu.data 1342.623498 # Average occupied blocks per requestor

448system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035675 # Average percentage of cache occupancy

446system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035675 # Average percentage of cache occupancy

449system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy
450system.cpu.l2cache.tags.occ_percent::total 0.051136 # Average percentage of cache occupancy
451system.cpu.l2cache.tags.occ_task_id_blocks::1024 2369 # Occupied blocks per task id
452system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
453system.cpu.l2cache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
454system.cpu.l2cache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id
455system.cpu.l2cache.tags.age_task_id_blocks_1024::3 322 # Occupied blocks per task id
456system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1679 # Occupied blocks per task id
457system.cpu.l2cache.tags.occ_task_id_percent::1024 0.072296 # Percentage of cache occupancy per task id
458system.cpu.l2cache.tags.tag_accesses 54045 # Number of tag accesses
459system.cpu.l2cache.tags.data_accesses 54045 # Number of data accesses
460system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states

447system.cpu.l2cache.tags.occ_percent::cpu.data 0.040974 # Average percentage of cache occupancy
448system.cpu.l2cache.tags.occ_percent::total 0.076649 # Average percentage of cache occupancy
449system.cpu.l2cache.tags.occ_task_id_blocks::1024 3453 # Occupied blocks per task id
450system.cpu.l2cache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id
451system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
452system.cpu.l2cache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id
453system.cpu.l2cache.tags.age_task_id_blocks_1024::3 536 # Occupied blocks per task id
454system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2517 # Occupied blocks per task id
455system.cpu.l2cache.tags.occ_task_id_percent::1024 0.105377 # Percentage of cache occupancy per task id
456system.cpu.l2cache.tags.tag_accesses 54029 # Number of tag accesses
457system.cpu.l2cache.tags.data_accesses 54029 # Number of data accesses
458system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states

461system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits
462system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits
463system.cpu.l2cache.WritebackClean_hits::writebacks 1448 # number of WritebackClean hits
464system.cpu.l2cache.WritebackClean_hits::total 1448 # number of WritebackClean hits
465system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
466system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
467system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1322 # number of ReadCleanReq hits
468system.cpu.l2cache.ReadCleanReq_hits::total 1322 # number of ReadCleanReq hits

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481system.cpu.l2cache.ReadSharedReq_misses::cpu.data 632 # number of ReadSharedReq misses
482system.cpu.l2cache.ReadSharedReq_misses::total 632 # number of ReadSharedReq misses
483system.cpu.l2cache.demand_misses::cpu.inst 1729 # number of demand (read+write) misses
484system.cpu.l2cache.demand_misses::cpu.data 1724 # number of demand (read+write) misses
485system.cpu.l2cache.demand_misses::total 3453 # number of demand (read+write) misses
486system.cpu.l2cache.overall_misses::cpu.inst 1729 # number of overall misses
487system.cpu.l2cache.overall_misses::cpu.data 1724 # number of overall misses
488system.cpu.l2cache.overall_misses::total 3453 # number of overall misses

459system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits
460system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits
461system.cpu.l2cache.WritebackClean_hits::writebacks 1448 # number of WritebackClean hits
462system.cpu.l2cache.WritebackClean_hits::total 1448 # number of WritebackClean hits
463system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits
464system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits
465system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1322 # number of ReadCleanReq hits
466system.cpu.l2cache.ReadCleanReq_hits::total 1322 # number of ReadCleanReq hits

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479system.cpu.l2cache.ReadSharedReq_misses::cpu.data 632 # number of ReadSharedReq misses
480system.cpu.l2cache.ReadSharedReq_misses::total 632 # number of ReadSharedReq misses
481system.cpu.l2cache.demand_misses::cpu.inst 1729 # number of demand (read+write) misses
482system.cpu.l2cache.demand_misses::cpu.data 1724 # number of demand (read+write) misses
483system.cpu.l2cache.demand_misses::total 3453 # number of demand (read+write) misses
484system.cpu.l2cache.overall_misses::cpu.inst 1729 # number of overall misses
485system.cpu.l2cache.overall_misses::cpu.data 1724 # number of overall misses
486system.cpu.l2cache.overall_misses::total 3453 # number of overall misses

489system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 65004500 # number of ReadExReq miss cycles
490system.cpu.l2cache.ReadExReq_miss_latency::total 65004500 # number of ReadExReq miss cycles
491system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 102968000 # number of ReadCleanReq miss cycles
492system.cpu.l2cache.ReadCleanReq_miss_latency::total 102968000 # number of ReadCleanReq miss cycles
493system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 37629500 # number of ReadSharedReq miss cycles
494system.cpu.l2cache.ReadSharedReq_miss_latency::total 37629500 # number of ReadSharedReq miss cycles
495system.cpu.l2cache.demand_miss_latency::cpu.inst 102968000 # number of demand (read+write) miss cycles
496system.cpu.l2cache.demand_miss_latency::cpu.data 102634000 # number of demand (read+write) miss cycles
497system.cpu.l2cache.demand_miss_latency::total 205602000 # number of demand (read+write) miss cycles
498system.cpu.l2cache.overall_miss_latency::cpu.inst 102968000 # number of overall miss cycles
499system.cpu.l2cache.overall_miss_latency::cpu.data 102634000 # number of overall miss cycles
500system.cpu.l2cache.overall_miss_latency::total 205602000 # number of overall miss cycles

487system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66096500 # number of ReadExReq miss cycles
488system.cpu.l2cache.ReadExReq_miss_latency::total 66096500 # number of ReadExReq miss cycles
489system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 104697000 # number of ReadCleanReq miss cycles
490system.cpu.l2cache.ReadCleanReq_miss_latency::total 104697000 # number of ReadCleanReq miss cycles
491system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 38261500 # number of ReadSharedReq miss cycles
492system.cpu.l2cache.ReadSharedReq_miss_latency::total 38261500 # number of ReadSharedReq miss cycles
493system.cpu.l2cache.demand_miss_latency::cpu.inst 104697000 # number of demand (read+write) miss cycles
494system.cpu.l2cache.demand_miss_latency::cpu.data 104358000 # number of demand (read+write) miss cycles
495system.cpu.l2cache.demand_miss_latency::total 209055000 # number of demand (read+write) miss cycles
496system.cpu.l2cache.overall_miss_latency::cpu.inst 104697000 # number of overall miss cycles
497system.cpu.l2cache.overall_miss_latency::cpu.data 104358000 # number of overall miss cycles
498system.cpu.l2cache.overall_miss_latency::total 209055000 # number of overall miss cycles

501system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses)
502system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses)
503system.cpu.l2cache.WritebackClean_accesses::writebacks 1448 # number of WritebackClean accesses(hits+misses)
504system.cpu.l2cache.WritebackClean_accesses::total 1448 # number of WritebackClean accesses(hits+misses)
505system.cpu.l2cache.ReadExReq_accesses::cpu.data 1100 # number of ReadExReq accesses(hits+misses)
506system.cpu.l2cache.ReadExReq_accesses::total 1100 # number of ReadExReq accesses(hits+misses)
507system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 3051 # number of ReadCleanReq accesses(hits+misses)
508system.cpu.l2cache.ReadCleanReq_accesses::total 3051 # number of ReadCleanReq accesses(hits+misses)

--- 12 unchanged lines hidden (view full) ---

521system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.917271 # miss rate for ReadSharedReq accesses
522system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.917271 # miss rate for ReadSharedReq accesses
523system.cpu.l2cache.demand_miss_rate::cpu.inst 0.566699 # miss rate for demand accesses
524system.cpu.l2cache.demand_miss_rate::cpu.data 0.963667 # miss rate for demand accesses
525system.cpu.l2cache.demand_miss_rate::total 0.713430 # miss rate for demand accesses
526system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses
527system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses
528system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses

499system.cpu.l2cache.WritebackDirty_accesses::writebacks 16 # number of WritebackDirty accesses(hits+misses)
500system.cpu.l2cache.WritebackDirty_accesses::total 16 # number of WritebackDirty accesses(hits+misses)
501system.cpu.l2cache.WritebackClean_accesses::writebacks 1448 # number of WritebackClean accesses(hits+misses)
502system.cpu.l2cache.WritebackClean_accesses::total 1448 # number of WritebackClean accesses(hits+misses)
503system.cpu.l2cache.ReadExReq_accesses::cpu.data 1100 # number of ReadExReq accesses(hits+misses)
504system.cpu.l2cache.ReadExReq_accesses::total 1100 # number of ReadExReq accesses(hits+misses)
505system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 3051 # number of ReadCleanReq accesses(hits+misses)
506system.cpu.l2cache.ReadCleanReq_accesses::total 3051 # number of ReadCleanReq accesses(hits+misses)

--- 12 unchanged lines hidden (view full) ---

519system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.917271 # miss rate for ReadSharedReq accesses
520system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.917271 # miss rate for ReadSharedReq accesses
521system.cpu.l2cache.demand_miss_rate::cpu.inst 0.566699 # miss rate for demand accesses
522system.cpu.l2cache.demand_miss_rate::cpu.data 0.963667 # miss rate for demand accesses
523system.cpu.l2cache.demand_miss_rate::total 0.713430 # miss rate for demand accesses
524system.cpu.l2cache.overall_miss_rate::cpu.inst 0.566699 # miss rate for overall accesses
525system.cpu.l2cache.overall_miss_rate::cpu.data 0.963667 # miss rate for overall accesses
526system.cpu.l2cache.overall_miss_rate::total 0.713430 # miss rate for overall accesses

529system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59527.930403 # average ReadExReq miss latency
530system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59527.930403 # average ReadExReq miss latency
531system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59553.499132 # average ReadCleanReq miss latency
532system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59553.499132 # average ReadCleanReq miss latency
533system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59540.348101 # average ReadSharedReq miss latency
534system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59540.348101 # average ReadSharedReq miss latency
535system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59553.499132 # average overall miss latency
536system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59532.482599 # average overall miss latency
537system.cpu.l2cache.demand_avg_miss_latency::total 59543.006082 # average overall miss latency
538system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59553.499132 # average overall miss latency
539system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59532.482599 # average overall miss latency
540system.cpu.l2cache.overall_avg_miss_latency::total 59543.006082 # average overall miss latency

527system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60527.930403 # average ReadExReq miss latency
528system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60527.930403 # average ReadExReq miss latency
529system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60553.499132 # average ReadCleanReq miss latency
530system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60553.499132 # average ReadCleanReq miss latency
531system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60540.348101 # average ReadSharedReq miss latency
532system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60540.348101 # average ReadSharedReq miss latency
533system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60553.499132 # average overall miss latency
534system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60532.482599 # average overall miss latency
535system.cpu.l2cache.demand_avg_miss_latency::total 60543.006082 # average overall miss latency
536system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60553.499132 # average overall miss latency
537system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60532.482599 # average overall miss latency
538system.cpu.l2cache.overall_avg_miss_latency::total 60543.006082 # average overall miss latency

541system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
542system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
543system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
544system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
545system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
546system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
547system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1092 # number of ReadExReq MSHR misses
548system.cpu.l2cache.ReadExReq_mshr_misses::total 1092 # number of ReadExReq MSHR misses
549system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1729 # number of ReadCleanReq MSHR misses
550system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1729 # number of ReadCleanReq MSHR misses
551system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 632 # number of ReadSharedReq MSHR misses
552system.cpu.l2cache.ReadSharedReq_mshr_misses::total 632 # number of ReadSharedReq MSHR misses
553system.cpu.l2cache.demand_mshr_misses::cpu.inst 1729 # number of demand (read+write) MSHR misses
554system.cpu.l2cache.demand_mshr_misses::cpu.data 1724 # number of demand (read+write) MSHR misses
555system.cpu.l2cache.demand_mshr_misses::total 3453 # number of demand (read+write) MSHR misses
556system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses
557system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses
558system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses

539system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
540system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
541system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
542system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
543system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
544system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
545system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1092 # number of ReadExReq MSHR misses
546system.cpu.l2cache.ReadExReq_mshr_misses::total 1092 # number of ReadExReq MSHR misses
547system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1729 # number of ReadCleanReq MSHR misses
548system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1729 # number of ReadCleanReq MSHR misses
549system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 632 # number of ReadSharedReq MSHR misses
550system.cpu.l2cache.ReadSharedReq_mshr_misses::total 632 # number of ReadSharedReq MSHR misses
551system.cpu.l2cache.demand_mshr_misses::cpu.inst 1729 # number of demand (read+write) MSHR misses
552system.cpu.l2cache.demand_mshr_misses::cpu.data 1724 # number of demand (read+write) MSHR misses
553system.cpu.l2cache.demand_mshr_misses::total 3453 # number of demand (read+write) MSHR misses
554system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses
555system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses
556system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses

559system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54084500 # number of ReadExReq MSHR miss cycles
560system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54084500 # number of ReadExReq MSHR miss cycles
561system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85678000 # number of ReadCleanReq MSHR miss cycles
562system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85678000 # number of ReadCleanReq MSHR miss cycles
563system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31309500 # number of ReadSharedReq MSHR miss cycles
564system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31309500 # number of ReadSharedReq MSHR miss cycles
565system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85678000 # number of demand (read+write) MSHR miss cycles
566system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85394000 # number of demand (read+write) MSHR miss cycles
567system.cpu.l2cache.demand_mshr_miss_latency::total 171072000 # number of demand (read+write) MSHR miss cycles
568system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85678000 # number of overall MSHR miss cycles
569system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85394000 # number of overall MSHR miss cycles
570system.cpu.l2cache.overall_mshr_miss_latency::total 171072000 # number of overall MSHR miss cycles

557system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 55176500 # number of ReadExReq MSHR miss cycles
558system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 55176500 # number of ReadExReq MSHR miss cycles
559system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 87407000 # number of ReadCleanReq MSHR miss cycles
560system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 87407000 # number of ReadCleanReq MSHR miss cycles
561system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31941500 # number of ReadSharedReq MSHR miss cycles
562system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31941500 # number of ReadSharedReq MSHR miss cycles
563system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87407000 # number of demand (read+write) MSHR miss cycles
564system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87118000 # number of demand (read+write) MSHR miss cycles
565system.cpu.l2cache.demand_mshr_miss_latency::total 174525000 # number of demand (read+write) MSHR miss cycles
566system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87407000 # number of overall MSHR miss cycles
567system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87118000 # number of overall MSHR miss cycles
568system.cpu.l2cache.overall_mshr_miss_latency::total 174525000 # number of overall MSHR miss cycles

571system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 # mshr miss rate for ReadExReq accesses
572system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992727 # mshr miss rate for ReadExReq accesses
573system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadCleanReq accesses
574system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.566699 # mshr miss rate for ReadCleanReq accesses
575system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadSharedReq accesses
576system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.917271 # mshr miss rate for ReadSharedReq accesses
577system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for demand accesses
578system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for demand accesses
579system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 # mshr miss rate for demand accesses
580system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses
581system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses
582system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses

569system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 # mshr miss rate for ReadExReq accesses
570system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.992727 # mshr miss rate for ReadExReq accesses
571system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadCleanReq accesses
572system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.566699 # mshr miss rate for ReadCleanReq accesses
573system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadSharedReq accesses
574system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.917271 # mshr miss rate for ReadSharedReq accesses
575system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for demand accesses
576system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for demand accesses
577system.cpu.l2cache.demand_mshr_miss_rate::total 0.713430 # mshr miss rate for demand accesses
578system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses
579system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses
580system.cpu.l2cache.overall_mshr_miss_rate::total 0.713430 # mshr miss rate for overall accesses

583system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49527.930403 # average ReadExReq mshr miss latency
584system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49527.930403 # average ReadExReq mshr miss latency
585system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49553.499132 # average ReadCleanReq mshr miss latency
586system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49553.499132 # average ReadCleanReq mshr miss latency
587system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49540.348101 # average ReadSharedReq mshr miss latency
588system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49540.348101 # average ReadSharedReq mshr miss latency
589system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49553.499132 # average overall mshr miss latency
590system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49532.482599 # average overall mshr miss latency
591system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49543.006082 # average overall mshr miss latency
592system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49553.499132 # average overall mshr miss latency
593system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49532.482599 # average overall mshr miss latency
594system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49543.006082 # average overall mshr miss latency

581system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50527.930403 # average ReadExReq mshr miss latency
582system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50527.930403 # average ReadExReq mshr miss latency
583system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50553.499132 # average ReadCleanReq mshr miss latency
584system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50553.499132 # average ReadCleanReq mshr miss latency
585system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50540.348101 # average ReadSharedReq mshr miss latency
586system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50540.348101 # average ReadSharedReq mshr miss latency
587system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50553.499132 # average overall mshr miss latency
588system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50532.482599 # average overall mshr miss latency
589system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50543.006082 # average overall mshr miss latency
590system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50553.499132 # average overall mshr miss latency
591system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50532.482599 # average overall mshr miss latency
592system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50543.006082 # average overall mshr miss latency

595system.cpu.toL2Bus.snoop_filter.tot_requests 6386 # Total number of requests made to the snoop filter.
596system.cpu.toL2Bus.snoop_filter.hit_single_requests 1644 # Number of requests hitting in the snoop filter with a single holder of the requested data.
597system.cpu.toL2Bus.snoop_filter.hit_multi_requests 64 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
598system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
599system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
600system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

593system.cpu.toL2Bus.snoop_filter.tot_requests 6386 # Total number of requests made to the snoop filter.
594system.cpu.toL2Bus.snoop_filter.hit_single_requests 1644 # Number of requests hitting in the snoop filter with a single holder of the requested data.
595system.cpu.toL2Bus.snoop_filter.hit_multi_requests 64 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
596system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
597system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
598system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

601system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states

599system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states

602system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution
603system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution
604system.cpu.toL2Bus.trans_dist::WritebackClean 1506 # Transaction distribution
605system.cpu.toL2Bus.trans_dist::CleanEvict 24 # Transaction distribution
606system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution
607system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution
608system.cpu.toL2Bus.trans_dist::ReadCleanReq 3051 # Transaction distribution
609system.cpu.toL2Bus.trans_dist::ReadSharedReq 689 # Transaction distribution

--- 17 unchanged lines hidden (view full) ---

627system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
628system.cpu.toL2Bus.snoop_fanout::total 4840 # Request fanout histogram
629system.cpu.toL2Bus.reqLayer0.occupancy 4715000 # Layer occupancy (ticks)
630system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
631system.cpu.toL2Bus.respLayer0.occupancy 4576500 # Layer occupancy (ticks)
632system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
633system.cpu.toL2Bus.respLayer1.occupancy 2683500 # Layer occupancy (ticks)
634system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)

600system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution
601system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution
602system.cpu.toL2Bus.trans_dist::WritebackClean 1506 # Transaction distribution
603system.cpu.toL2Bus.trans_dist::CleanEvict 24 # Transaction distribution
604system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution
605system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution
606system.cpu.toL2Bus.trans_dist::ReadCleanReq 3051 # Transaction distribution
607system.cpu.toL2Bus.trans_dist::ReadSharedReq 689 # Transaction distribution

--- 17 unchanged lines hidden (view full) ---

625system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
626system.cpu.toL2Bus.snoop_fanout::total 4840 # Request fanout histogram
627system.cpu.toL2Bus.reqLayer0.occupancy 4715000 # Layer occupancy (ticks)
628system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
629system.cpu.toL2Bus.respLayer0.occupancy 4576500 # Layer occupancy (ticks)
630system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
631system.cpu.toL2Bus.respLayer1.occupancy 2683500 # Layer occupancy (ticks)
632system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)

635system.membus.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states

633system.membus.snoop_filter.tot_requests 3453 # Total number of requests made to the snoop filter.
634system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
635system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
636system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
637system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
638system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
639system.membus.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states