| stats.txt (11515:c48c7cc5a522) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.230198 # Number of seconds simulated 4sim_ticks 230197694500 # Number of ticks simulated 5final_tick 230197694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.230198 # Number of seconds simulated 4sim_ticks 230197694500 # Number of ticks simulated 5final_tick 230197694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1495549 # Simulator instruction rate (inst/s) 8host_op_rate 1576687 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2003415873 # Simulator tick rate (ticks/s) 10host_mem_usage 314964 # Number of bytes of host memory used 11host_seconds 114.90 # Real time elapsed on the host | 7host_inst_rate 1499491 # Simulator instruction rate (inst/s) 8host_op_rate 1580842 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2008696236 # Simulator tick rate (ticks/s) 10host_mem_usage 315632 # Number of bytes of host memory used 11host_seconds 114.60 # Real time elapsed on the host |
| 12sim_insts 171842484 # Number of instructions simulated 13sim_ops 181165371 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 171842484 # Number of instructions simulated 13sim_ops 181165371 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory 18system.physmem.bytes_read::total 220992 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 110656 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 110656 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 480700 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 479310 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 960010 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 480700 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 480700 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 480700 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 479310 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 960010 # Total bandwidth to/from this memory (bytes/s) | 17system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory 19system.physmem.bytes_read::total 220992 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 110656 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 110656 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 480700 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 479310 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 960010 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 480700 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 480700 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 480700 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 479310 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 960010 # Total bandwidth to/from this memory (bytes/s) |
| 33system.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states |
|
| 32system.cpu_clk_domain.clock 500 # Clock period in ticks | 34system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 35system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states |
|
| 33system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 34system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 36system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 54system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 55system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 56system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 57system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 58system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 59system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 60system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 61system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 36system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 57system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 58system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 59system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 60system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 61system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 62system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 63system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 64system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 65system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states |
|
| 62system.cpu.dtb.walker.walks 0 # Table walker walks requested 63system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 64system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 65system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 66system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 67system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 68system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 69system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 83system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 84system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 85system.cpu.dtb.read_accesses 0 # DTB read accesses 86system.cpu.dtb.write_accesses 0 # DTB write accesses 87system.cpu.dtb.inst_accesses 0 # ITB inst accesses 88system.cpu.dtb.hits 0 # DTB hits 89system.cpu.dtb.misses 0 # DTB misses 90system.cpu.dtb.accesses 0 # DTB accesses | 66system.cpu.dtb.walker.walks 0 # Table walker walks requested 67system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 68system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 69system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 70system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 71system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 72system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 73system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 87system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 88system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 89system.cpu.dtb.read_accesses 0 # DTB read accesses 90system.cpu.dtb.write_accesses 0 # DTB write accesses 91system.cpu.dtb.inst_accesses 0 # ITB inst accesses 92system.cpu.dtb.hits 0 # DTB hits 93system.cpu.dtb.misses 0 # DTB misses 94system.cpu.dtb.accesses 0 # DTB accesses |
| 95system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states |
|
| 91system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 92system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 93system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 94system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 95system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 96system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 112system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 113system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 114system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 115system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 116system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 117system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 118system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 119system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 96system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 117system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 118system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 119system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 120system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 121system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 122system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 123system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 124system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 125system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states |
|
| 120system.cpu.itb.walker.walks 0 # Table walker walks requested 121system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 122system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 123system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 124system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 125system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 126system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 127system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 142system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 143system.cpu.itb.read_accesses 0 # DTB read accesses 144system.cpu.itb.write_accesses 0 # DTB write accesses 145system.cpu.itb.inst_accesses 0 # ITB inst accesses 146system.cpu.itb.hits 0 # DTB hits 147system.cpu.itb.misses 0 # DTB misses 148system.cpu.itb.accesses 0 # DTB accesses 149system.cpu.workload.num_syscalls 400 # Number of system calls | 126system.cpu.itb.walker.walks 0 # Table walker walks requested 127system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 128system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 129system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 130system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 131system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 132system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 133system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 148system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 149system.cpu.itb.read_accesses 0 # DTB read accesses 150system.cpu.itb.write_accesses 0 # DTB write accesses 151system.cpu.itb.inst_accesses 0 # ITB inst accesses 152system.cpu.itb.hits 0 # DTB hits 153system.cpu.itb.misses 0 # DTB misses 154system.cpu.itb.accesses 0 # DTB accesses 155system.cpu.workload.num_syscalls 400 # Number of system calls |
| 156system.cpu.pwrStateResidencyTicks::ON 230197694500 # Cumulative time (in ticks) in various power states |
|
| 150system.cpu.numCycles 460395389 # number of cpu cycles simulated 151system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 152system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 153system.cpu.committedInsts 171842484 # Number of instructions committed 154system.cpu.committedOps 181165371 # Number of ops (including micro ops) committed 155system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses 156system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses 157system.cpu.num_func_calls 3545028 # number of times a function call or return occured --- 44 unchanged lines hidden (view full) --- 202system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction 203system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction 204system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction 205system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction 206system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction 207system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 208system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 209system.cpu.op_class::total 181650743 # Class of executed instruction | 157system.cpu.numCycles 460395389 # number of cpu cycles simulated 158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 160system.cpu.committedInsts 171842484 # Number of instructions committed 161system.cpu.committedOps 181165371 # Number of ops (including micro ops) committed 162system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses 163system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses 164system.cpu.num_func_calls 3545028 # number of times a function call or return occured --- 44 unchanged lines hidden (view full) --- 209system.cpu.op_class::SimdFloatMult 200806 0.11% 77.64% # Class of executed instruction 210system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction 211system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction 212system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction 213system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction 214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 216system.cpu.op_class::total 181650743 # Class of executed instruction |
| 217system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states |
|
| 210system.cpu.dcache.tags.replacements 40 # number of replacements 211system.cpu.dcache.tags.tagsinuse 1363.571253 # Cycle average of tags in use 212system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. 213system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. 214system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks. 215system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 216system.cpu.dcache.tags.occ_blocks::cpu.data 1363.571253 # Average occupied blocks per requestor 217system.cpu.dcache.tags.occ_percent::cpu.data 0.332903 # Average percentage of cache occupancy 218system.cpu.dcache.tags.occ_percent::total 0.332903 # Average percentage of cache occupancy 219system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id 220system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id 221system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id 222system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id 223system.cpu.dcache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id 224system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 # Occupied blocks per task id 225system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 # Percentage of cache occupancy per task id 226system.cpu.dcache.tags.tag_accesses 80330619 # Number of tag accesses 227system.cpu.dcache.tags.data_accesses 80330619 # Number of data accesses | 218system.cpu.dcache.tags.replacements 40 # number of replacements 219system.cpu.dcache.tags.tagsinuse 1363.571253 # Cycle average of tags in use 220system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. 221system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. 222system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks. 223system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 224system.cpu.dcache.tags.occ_blocks::cpu.data 1363.571253 # Average occupied blocks per requestor 225system.cpu.dcache.tags.occ_percent::cpu.data 0.332903 # Average percentage of cache occupancy 226system.cpu.dcache.tags.occ_percent::total 0.332903 # Average percentage of cache occupancy 227system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id 228system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id 229system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id 230system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id 231system.cpu.dcache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id 232system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 # Occupied blocks per task id 233system.cpu.dcache.tags.occ_task_id_percent::1024 0.427002 # Percentage of cache occupancy per task id 234system.cpu.dcache.tags.tag_accesses 80330619 # Number of tag accesses 235system.cpu.dcache.tags.data_accesses 80330619 # Number of data accesses |
| 236system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states |
|
| 228system.cpu.dcache.ReadReq_hits::cpu.data 27754163 # number of ReadReq hits 229system.cpu.dcache.ReadReq_hits::total 27754163 # number of ReadReq hits 230system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits 231system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits 232system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits 233system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits 234system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits 235system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits --- 96 unchanged lines hidden (view full) --- 332system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60671.363636 # average WriteReq mshr miss latency 333system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60671.363636 # average WriteReq mshr miss latency 334system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency 335system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency 336system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59278.803132 # average overall mshr miss latency 337system.cpu.dcache.demand_avg_mshr_miss_latency::total 59278.803132 # average overall mshr miss latency 338system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59279.765232 # average overall mshr miss latency 339system.cpu.dcache.overall_avg_mshr_miss_latency::total 59279.765232 # average overall mshr miss latency | 237system.cpu.dcache.ReadReq_hits::cpu.data 27754163 # number of ReadReq hits 238system.cpu.dcache.ReadReq_hits::total 27754163 # number of ReadReq hits 239system.cpu.dcache.WriteReq_hits::cpu.data 12363187 # number of WriteReq hits 240system.cpu.dcache.WriteReq_hits::total 12363187 # number of WriteReq hits 241system.cpu.dcache.SoftPFReq_hits::cpu.data 462 # number of SoftPFReq hits 242system.cpu.dcache.SoftPFReq_hits::total 462 # number of SoftPFReq hits 243system.cpu.dcache.LoadLockedReq_hits::cpu.data 22407 # number of LoadLockedReq hits 244system.cpu.dcache.LoadLockedReq_hits::total 22407 # number of LoadLockedReq hits --- 96 unchanged lines hidden (view full) --- 341system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60671.363636 # average WriteReq mshr miss latency 342system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60671.363636 # average WriteReq mshr miss latency 343system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency 344system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency 345system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59278.803132 # average overall mshr miss latency 346system.cpu.dcache.demand_avg_mshr_miss_latency::total 59278.803132 # average overall mshr miss latency 347system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59279.765232 # average overall mshr miss latency 348system.cpu.dcache.overall_avg_mshr_miss_latency::total 59279.765232 # average overall mshr miss latency |
| 349system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states |
|
| 340system.cpu.icache.tags.replacements 1506 # number of replacements 341system.cpu.icache.tags.tagsinuse 1147.958164 # Cycle average of tags in use 342system.cpu.icache.tags.total_refs 189857002 # Total number of references to valid blocks. 343system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks. 344system.cpu.icache.tags.avg_refs 62227.794821 # Average number of references to valid blocks. 345system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 346system.cpu.icache.tags.occ_blocks::cpu.inst 1147.958164 # Average occupied blocks per requestor 347system.cpu.icache.tags.occ_percent::cpu.inst 0.560526 # Average percentage of cache occupancy 348system.cpu.icache.tags.occ_percent::total 0.560526 # Average percentage of cache occupancy 349system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id 350system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id 351system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id 352system.cpu.icache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id 353system.cpu.icache.tags.age_task_id_blocks_1024::3 270 # Occupied blocks per task id 354system.cpu.icache.tags.age_task_id_blocks_1024::4 942 # Occupied blocks per task id 355system.cpu.icache.tags.occ_task_id_percent::1024 0.754395 # Percentage of cache occupancy per task id 356system.cpu.icache.tags.tag_accesses 379723157 # Number of tag accesses 357system.cpu.icache.tags.data_accesses 379723157 # Number of data accesses | 350system.cpu.icache.tags.replacements 1506 # number of replacements 351system.cpu.icache.tags.tagsinuse 1147.958164 # Cycle average of tags in use 352system.cpu.icache.tags.total_refs 189857002 # Total number of references to valid blocks. 353system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks. 354system.cpu.icache.tags.avg_refs 62227.794821 # Average number of references to valid blocks. 355system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 356system.cpu.icache.tags.occ_blocks::cpu.inst 1147.958164 # Average occupied blocks per requestor 357system.cpu.icache.tags.occ_percent::cpu.inst 0.560526 # Average percentage of cache occupancy 358system.cpu.icache.tags.occ_percent::total 0.560526 # Average percentage of cache occupancy 359system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id 360system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id 361system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id 362system.cpu.icache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id 363system.cpu.icache.tags.age_task_id_blocks_1024::3 270 # Occupied blocks per task id 364system.cpu.icache.tags.age_task_id_blocks_1024::4 942 # Occupied blocks per task id 365system.cpu.icache.tags.occ_task_id_percent::1024 0.754395 # Percentage of cache occupancy per task id 366system.cpu.icache.tags.tag_accesses 379723157 # Number of tag accesses 367system.cpu.icache.tags.data_accesses 379723157 # Number of data accesses |
| 368system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states |
|
| 358system.cpu.icache.ReadReq_hits::cpu.inst 189857002 # number of ReadReq hits 359system.cpu.icache.ReadReq_hits::total 189857002 # number of ReadReq hits 360system.cpu.icache.demand_hits::cpu.inst 189857002 # number of demand (read+write) hits 361system.cpu.icache.demand_hits::total 189857002 # number of demand (read+write) hits 362system.cpu.icache.overall_hits::cpu.inst 189857002 # number of overall hits 363system.cpu.icache.overall_hits::total 189857002 # number of overall hits 364system.cpu.icache.ReadReq_misses::cpu.inst 3051 # number of ReadReq misses 365system.cpu.icache.ReadReq_misses::total 3051 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 418system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses 419system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses 420system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39836.447067 # average ReadReq mshr miss latency 421system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39836.447067 # average ReadReq mshr miss latency 422system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency 423system.cpu.icache.demand_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency 424system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency 425system.cpu.icache.overall_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency | 369system.cpu.icache.ReadReq_hits::cpu.inst 189857002 # number of ReadReq hits 370system.cpu.icache.ReadReq_hits::total 189857002 # number of ReadReq hits 371system.cpu.icache.demand_hits::cpu.inst 189857002 # number of demand (read+write) hits 372system.cpu.icache.demand_hits::total 189857002 # number of demand (read+write) hits 373system.cpu.icache.overall_hits::cpu.inst 189857002 # number of overall hits 374system.cpu.icache.overall_hits::total 189857002 # number of overall hits 375system.cpu.icache.ReadReq_misses::cpu.inst 3051 # number of ReadReq misses 376system.cpu.icache.ReadReq_misses::total 3051 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 429system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses 430system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses 431system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39836.447067 # average ReadReq mshr miss latency 432system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39836.447067 # average ReadReq mshr miss latency 433system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency 434system.cpu.icache.demand_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency 435system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency 436system.cpu.icache.overall_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency |
| 437system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states |
|
| 426system.cpu.l2cache.tags.replacements 0 # number of replacements 427system.cpu.l2cache.tags.tagsinuse 1675.610098 # Cycle average of tags in use 428system.cpu.l2cache.tags.total_refs 2846 # Total number of references to valid blocks. 429system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks. 430system.cpu.l2cache.tags.avg_refs 1.201351 # Average number of references to valid blocks. 431system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 432system.cpu.l2cache.tags.occ_blocks::writebacks 3.037805 # Average occupied blocks per requestor 433system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.001518 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 440system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 441system.cpu.l2cache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id 442system.cpu.l2cache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id 443system.cpu.l2cache.tags.age_task_id_blocks_1024::3 322 # Occupied blocks per task id 444system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1679 # Occupied blocks per task id 445system.cpu.l2cache.tags.occ_task_id_percent::1024 0.072296 # Percentage of cache occupancy per task id 446system.cpu.l2cache.tags.tag_accesses 54045 # Number of tag accesses 447system.cpu.l2cache.tags.data_accesses 54045 # Number of data accesses | 438system.cpu.l2cache.tags.replacements 0 # number of replacements 439system.cpu.l2cache.tags.tagsinuse 1675.610098 # Cycle average of tags in use 440system.cpu.l2cache.tags.total_refs 2846 # Total number of references to valid blocks. 441system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks. 442system.cpu.l2cache.tags.avg_refs 1.201351 # Average number of references to valid blocks. 443system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 444system.cpu.l2cache.tags.occ_blocks::writebacks 3.037805 # Average occupied blocks per requestor 445system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.001518 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 452system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id 453system.cpu.l2cache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id 454system.cpu.l2cache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id 455system.cpu.l2cache.tags.age_task_id_blocks_1024::3 322 # Occupied blocks per task id 456system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1679 # Occupied blocks per task id 457system.cpu.l2cache.tags.occ_task_id_percent::1024 0.072296 # Percentage of cache occupancy per task id 458system.cpu.l2cache.tags.tag_accesses 54045 # Number of tag accesses 459system.cpu.l2cache.tags.data_accesses 54045 # Number of data accesses |
| 460system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states |
|
| 448system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits 449system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits 450system.cpu.l2cache.WritebackClean_hits::writebacks 1448 # number of WritebackClean hits 451system.cpu.l2cache.WritebackClean_hits::total 1448 # number of WritebackClean hits 452system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits 453system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits 454system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1322 # number of ReadCleanReq hits 455system.cpu.l2cache.ReadCleanReq_hits::total 1322 # number of ReadCleanReq hits --- 124 unchanged lines hidden (view full) --- 580system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49532.482599 # average overall mshr miss latency 581system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49543.006082 # average overall mshr miss latency 582system.cpu.toL2Bus.snoop_filter.tot_requests 6386 # Total number of requests made to the snoop filter. 583system.cpu.toL2Bus.snoop_filter.hit_single_requests 1644 # Number of requests hitting in the snoop filter with a single holder of the requested data. 584system.cpu.toL2Bus.snoop_filter.hit_multi_requests 64 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 585system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 586system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 587system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 461system.cpu.l2cache.WritebackDirty_hits::writebacks 16 # number of WritebackDirty hits 462system.cpu.l2cache.WritebackDirty_hits::total 16 # number of WritebackDirty hits 463system.cpu.l2cache.WritebackClean_hits::writebacks 1448 # number of WritebackClean hits 464system.cpu.l2cache.WritebackClean_hits::total 1448 # number of WritebackClean hits 465system.cpu.l2cache.ReadExReq_hits::cpu.data 8 # number of ReadExReq hits 466system.cpu.l2cache.ReadExReq_hits::total 8 # number of ReadExReq hits 467system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1322 # number of ReadCleanReq hits 468system.cpu.l2cache.ReadCleanReq_hits::total 1322 # number of ReadCleanReq hits --- 124 unchanged lines hidden (view full) --- 593system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49532.482599 # average overall mshr miss latency 594system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49543.006082 # average overall mshr miss latency 595system.cpu.toL2Bus.snoop_filter.tot_requests 6386 # Total number of requests made to the snoop filter. 596system.cpu.toL2Bus.snoop_filter.hit_single_requests 1644 # Number of requests hitting in the snoop filter with a single holder of the requested data. 597system.cpu.toL2Bus.snoop_filter.hit_multi_requests 64 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 598system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 599system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 600system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 601system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states |
|
| 588system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution 589system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution 590system.cpu.toL2Bus.trans_dist::WritebackClean 1506 # Transaction distribution 591system.cpu.toL2Bus.trans_dist::CleanEvict 24 # Transaction distribution 592system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution 593system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution 594system.cpu.toL2Bus.trans_dist::ReadCleanReq 3051 # Transaction distribution 595system.cpu.toL2Bus.trans_dist::ReadSharedReq 689 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 612system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 613system.cpu.toL2Bus.snoop_fanout::total 4840 # Request fanout histogram 614system.cpu.toL2Bus.reqLayer0.occupancy 4715000 # Layer occupancy (ticks) 615system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 616system.cpu.toL2Bus.respLayer0.occupancy 4576500 # Layer occupancy (ticks) 617system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 618system.cpu.toL2Bus.respLayer1.occupancy 2683500 # Layer occupancy (ticks) 619system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) | 602system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution 603system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution 604system.cpu.toL2Bus.trans_dist::WritebackClean 1506 # Transaction distribution 605system.cpu.toL2Bus.trans_dist::CleanEvict 24 # Transaction distribution 606system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution 607system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution 608system.cpu.toL2Bus.trans_dist::ReadCleanReq 3051 # Transaction distribution 609system.cpu.toL2Bus.trans_dist::ReadSharedReq 689 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 626system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 627system.cpu.toL2Bus.snoop_fanout::total 4840 # Request fanout histogram 628system.cpu.toL2Bus.reqLayer0.occupancy 4715000 # Layer occupancy (ticks) 629system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) 630system.cpu.toL2Bus.respLayer0.occupancy 4576500 # Layer occupancy (ticks) 631system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 632system.cpu.toL2Bus.respLayer1.occupancy 2683500 # Layer occupancy (ticks) 633system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) |
| 634system.membus.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states |
|
| 620system.membus.trans_dist::ReadResp 2361 # Transaction distribution 621system.membus.trans_dist::ReadExReq 1092 # Transaction distribution 622system.membus.trans_dist::ReadExResp 1092 # Transaction distribution 623system.membus.trans_dist::ReadSharedReq 2361 # Transaction distribution 624system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 # Packet count per connected master and slave (bytes) 625system.membus.pkt_count::total 6906 # Packet count per connected master and slave (bytes) 626system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes) 627system.membus.pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- | 635system.membus.trans_dist::ReadResp 2361 # Transaction distribution 636system.membus.trans_dist::ReadExReq 1092 # Transaction distribution 637system.membus.trans_dist::ReadExResp 1092 # Transaction distribution 638system.membus.trans_dist::ReadSharedReq 2361 # Transaction distribution 639system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6906 # Packet count per connected master and slave (bytes) 640system.membus.pkt_count::total 6906 # Packet count per connected master and slave (bytes) 641system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 220992 # Cumulative packet size per connected master and slave (bytes) 642system.membus.pkt_size::total 220992 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- |