| stats.txt (11336:b318499f676c) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.230198 # Number of seconds simulated 4sim_ticks 230197694500 # Number of ticks simulated 5final_tick 230197694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.230198 # Number of seconds simulated 4sim_ticks 230197694500 # Number of ticks simulated 5final_tick 230197694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 1151849 # Simulator instruction rate (inst/s) 8host_op_rate 1214340 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1543000471 # Simulator tick rate (ticks/s) 10host_mem_usage 272972 # Number of bytes of host memory used 11host_seconds 149.19 # Real time elapsed on the host | 7host_inst_rate 927075 # Simulator instruction rate (inst/s) 8host_op_rate 977372 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1241896591 # Simulator tick rate (ticks/s) 10host_mem_usage 272260 # Number of bytes of host memory used 11host_seconds 185.36 # Real time elapsed on the host |
| 12sim_insts 171842484 # Number of instructions simulated 13sim_ops 181165371 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory 18system.physmem.bytes_read::total 220992 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 110656 # Number of instructions bytes read from this memory --- 270 unchanged lines hidden (view full) --- 290system.cpu.dcache.overall_avg_miss_latency::cpu.data 60245.108999 # average overall miss latency 291system.cpu.dcache.overall_avg_miss_latency::total 60245.108999 # average overall miss latency 292system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 293system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 294system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 295system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 296system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 297system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 171842484 # Number of instructions simulated 13sim_ops 181165371 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory 18system.physmem.bytes_read::total 220992 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 110656 # Number of instructions bytes read from this memory --- 270 unchanged lines hidden (view full) --- 290system.cpu.dcache.overall_avg_miss_latency::cpu.data 60245.108999 # average overall miss latency 291system.cpu.dcache.overall_avg_miss_latency::total 60245.108999 # average overall miss latency 292system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 293system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 294system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 295system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 296system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 297system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 298system.cpu.dcache.fast_writes 0 # number of fast writes performed 299system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 300system.cpu.dcache.writebacks::writebacks 16 # number of writebacks 301system.cpu.dcache.writebacks::total 16 # number of writebacks 302system.cpu.dcache.ReadReq_mshr_misses::cpu.data 688 # number of ReadReq MSHR misses 303system.cpu.dcache.ReadReq_mshr_misses::total 688 # number of ReadReq MSHR misses 304system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses 305system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses 306system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 307system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses --- 26 unchanged lines hidden (view full) --- 334system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60671.363636 # average WriteReq mshr miss latency 335system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60671.363636 # average WriteReq mshr miss latency 336system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency 337system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency 338system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59278.803132 # average overall mshr miss latency 339system.cpu.dcache.demand_avg_mshr_miss_latency::total 59278.803132 # average overall mshr miss latency 340system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59279.765232 # average overall mshr miss latency 341system.cpu.dcache.overall_avg_mshr_miss_latency::total 59279.765232 # average overall mshr miss latency | 298system.cpu.dcache.writebacks::writebacks 16 # number of writebacks 299system.cpu.dcache.writebacks::total 16 # number of writebacks 300system.cpu.dcache.ReadReq_mshr_misses::cpu.data 688 # number of ReadReq MSHR misses 301system.cpu.dcache.ReadReq_mshr_misses::total 688 # number of ReadReq MSHR misses 302system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses 303system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses 304system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 305system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses --- 26 unchanged lines hidden (view full) --- 332system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60671.363636 # average WriteReq mshr miss latency 333system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60671.363636 # average WriteReq mshr miss latency 334system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency 335system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency 336system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59278.803132 # average overall mshr miss latency 337system.cpu.dcache.demand_avg_mshr_miss_latency::total 59278.803132 # average overall mshr miss latency 338system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59279.765232 # average overall mshr miss latency 339system.cpu.dcache.overall_avg_mshr_miss_latency::total 59279.765232 # average overall mshr miss latency |
| 342system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 343system.cpu.icache.tags.replacements 1506 # number of replacements 344system.cpu.icache.tags.tagsinuse 1147.958164 # Cycle average of tags in use 345system.cpu.icache.tags.total_refs 189857002 # Total number of references to valid blocks. 346system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks. 347system.cpu.icache.tags.avg_refs 62227.794821 # Average number of references to valid blocks. 348system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 349system.cpu.icache.tags.occ_blocks::cpu.inst 1147.958164 # Average occupied blocks per requestor 350system.cpu.icache.tags.occ_percent::cpu.inst 0.560526 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 395system.cpu.icache.overall_avg_miss_latency::cpu.inst 40836.447067 # average overall miss latency 396system.cpu.icache.overall_avg_miss_latency::total 40836.447067 # average overall miss latency 397system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 398system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 399system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 400system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 401system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 402system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 340system.cpu.icache.tags.replacements 1506 # number of replacements 341system.cpu.icache.tags.tagsinuse 1147.958164 # Cycle average of tags in use 342system.cpu.icache.tags.total_refs 189857002 # Total number of references to valid blocks. 343system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks. 344system.cpu.icache.tags.avg_refs 62227.794821 # Average number of references to valid blocks. 345system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 346system.cpu.icache.tags.occ_blocks::cpu.inst 1147.958164 # Average occupied blocks per requestor 347system.cpu.icache.tags.occ_percent::cpu.inst 0.560526 # Average percentage of cache occupancy --- 44 unchanged lines hidden (view full) --- 392system.cpu.icache.overall_avg_miss_latency::cpu.inst 40836.447067 # average overall miss latency 393system.cpu.icache.overall_avg_miss_latency::total 40836.447067 # average overall miss latency 394system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 395system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 396system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 397system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 398system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 399system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 403system.cpu.icache.fast_writes 0 # number of fast writes performed 404system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 405system.cpu.icache.writebacks::writebacks 1506 # number of writebacks 406system.cpu.icache.writebacks::total 1506 # number of writebacks 407system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3051 # number of ReadReq MSHR misses 408system.cpu.icache.ReadReq_mshr_misses::total 3051 # number of ReadReq MSHR misses 409system.cpu.icache.demand_mshr_misses::cpu.inst 3051 # number of demand (read+write) MSHR misses 410system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses 411system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses 412system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 423system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses 424system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses 425system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39836.447067 # average ReadReq mshr miss latency 426system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39836.447067 # average ReadReq mshr miss latency 427system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency 428system.cpu.icache.demand_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency 429system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency 430system.cpu.icache.overall_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency | 400system.cpu.icache.writebacks::writebacks 1506 # number of writebacks 401system.cpu.icache.writebacks::total 1506 # number of writebacks 402system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3051 # number of ReadReq MSHR misses 403system.cpu.icache.ReadReq_mshr_misses::total 3051 # number of ReadReq MSHR misses 404system.cpu.icache.demand_mshr_misses::cpu.inst 3051 # number of demand (read+write) MSHR misses 405system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses 406system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses 407system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 418system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses 419system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses 420system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39836.447067 # average ReadReq mshr miss latency 421system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39836.447067 # average ReadReq mshr miss latency 422system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency 423system.cpu.icache.demand_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency 424system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency 425system.cpu.icache.overall_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency |
| 431system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 432system.cpu.l2cache.tags.replacements 0 # number of replacements 433system.cpu.l2cache.tags.tagsinuse 1675.610098 # Cycle average of tags in use 434system.cpu.l2cache.tags.total_refs 2846 # Total number of references to valid blocks. 435system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks. 436system.cpu.l2cache.tags.avg_refs 1.201351 # Average number of references to valid blocks. 437system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 438system.cpu.l2cache.tags.occ_blocks::writebacks 3.037805 # Average occupied blocks per requestor 439system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.001518 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 532system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59532.482599 # average overall miss latency 533system.cpu.l2cache.overall_avg_miss_latency::total 59543.006082 # average overall miss latency 534system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 535system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 536system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 537system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 538system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 539system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 426system.cpu.l2cache.tags.replacements 0 # number of replacements 427system.cpu.l2cache.tags.tagsinuse 1675.610098 # Cycle average of tags in use 428system.cpu.l2cache.tags.total_refs 2846 # Total number of references to valid blocks. 429system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks. 430system.cpu.l2cache.tags.avg_refs 1.201351 # Average number of references to valid blocks. 431system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 432system.cpu.l2cache.tags.occ_blocks::writebacks 3.037805 # Average occupied blocks per requestor 433system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.001518 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 526system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59532.482599 # average overall miss latency 527system.cpu.l2cache.overall_avg_miss_latency::total 59543.006082 # average overall miss latency 528system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 529system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 530system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 531system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 532system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 533system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 540system.cpu.l2cache.fast_writes 0 # number of fast writes performed 541system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 542system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1092 # number of ReadExReq MSHR misses 543system.cpu.l2cache.ReadExReq_mshr_misses::total 1092 # number of ReadExReq MSHR misses 544system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1729 # number of ReadCleanReq MSHR misses 545system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1729 # number of ReadCleanReq MSHR misses 546system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 632 # number of ReadSharedReq MSHR misses 547system.cpu.l2cache.ReadSharedReq_mshr_misses::total 632 # number of ReadSharedReq MSHR misses 548system.cpu.l2cache.demand_mshr_misses::cpu.inst 1729 # number of demand (read+write) MSHR misses 549system.cpu.l2cache.demand_mshr_misses::cpu.data 1724 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 582system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49540.348101 # average ReadSharedReq mshr miss latency 583system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49540.348101 # average ReadSharedReq mshr miss latency 584system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49553.499132 # average overall mshr miss latency 585system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49532.482599 # average overall mshr miss latency 586system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49543.006082 # average overall mshr miss latency 587system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49553.499132 # average overall mshr miss latency 588system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49532.482599 # average overall mshr miss latency 589system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49543.006082 # average overall mshr miss latency | 534system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1092 # number of ReadExReq MSHR misses 535system.cpu.l2cache.ReadExReq_mshr_misses::total 1092 # number of ReadExReq MSHR misses 536system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1729 # number of ReadCleanReq MSHR misses 537system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1729 # number of ReadCleanReq MSHR misses 538system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 632 # number of ReadSharedReq MSHR misses 539system.cpu.l2cache.ReadSharedReq_mshr_misses::total 632 # number of ReadSharedReq MSHR misses 540system.cpu.l2cache.demand_mshr_misses::cpu.inst 1729 # number of demand (read+write) MSHR misses 541system.cpu.l2cache.demand_mshr_misses::cpu.data 1724 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 574system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49540.348101 # average ReadSharedReq mshr miss latency 575system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49540.348101 # average ReadSharedReq mshr miss latency 576system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49553.499132 # average overall mshr miss latency 577system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49532.482599 # average overall mshr miss latency 578system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49543.006082 # average overall mshr miss latency 579system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49553.499132 # average overall mshr miss latency 580system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49532.482599 # average overall mshr miss latency 581system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49543.006082 # average overall mshr miss latency |
| 590system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 591system.cpu.toL2Bus.snoop_filter.tot_requests 6386 # Total number of requests made to the snoop filter. 592system.cpu.toL2Bus.snoop_filter.hit_single_requests 1644 # Number of requests hitting in the snoop filter with a single holder of the requested data. 593system.cpu.toL2Bus.snoop_filter.hit_multi_requests 64 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 594system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 595system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 596system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 597system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution 598system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution --- 55 unchanged lines hidden --- | 582system.cpu.toL2Bus.snoop_filter.tot_requests 6386 # Total number of requests made to the snoop filter. 583system.cpu.toL2Bus.snoop_filter.hit_single_requests 1644 # Number of requests hitting in the snoop filter with a single holder of the requested data. 584system.cpu.toL2Bus.snoop_filter.hit_multi_requests 64 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 585system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 586system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 587system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 588system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution 589system.cpu.toL2Bus.trans_dist::WritebackDirty 16 # Transaction distribution --- 55 unchanged lines hidden --- |