Cross Reference: /gem5/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 0.230173 # Number of seconds simulated
4sim_ticks 230173358500 # Number of ticks simulated
5final_tick 230173358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 0.230174 # Number of seconds simulated
4sim_ticks 230173520500 # Number of ticks simulated
5final_tick 230173520500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 1194511 # Simulator instruction rate (inst/s)
8host_op_rate 1259316 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1599980237 # Simulator tick rate (ticks/s)
10host_mem_usage 316228 # Number of bytes of host memory used
11host_seconds 143.86 # Real time elapsed on the host

7host_inst_rate 1035845 # Simulator instruction rate (inst/s)
8host_op_rate 1092042 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1387457275 # Simulator tick rate (ticks/s)
10host_mem_usage 319880 # Number of bytes of host memory used
11host_seconds 165.90 # Real time elapsed on the host

12sim_insts 171842484 # Number of instructions simulated
13sim_ops 181165371 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 110336 # Number of bytes read from this memory
18system.physmem.bytes_read::total 220992 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 110656 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 110656 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 1729 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 1724 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 3453 # Number of read requests responded to by this memory

24system.physmem.bw_read::cpu.inst 480751 # Total read bandwidth from this memory (bytes/s)

24system.physmem.bw_read::cpu.inst 480750 # Total read bandwidth from this memory (bytes/s)

25system.physmem.bw_read::cpu.data 479360 # Total read bandwidth from this memory (bytes/s)

26system.physmem.bw_read::total 960111 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 480751 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 480751 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 480751 # Total bandwidth to/from this memory (bytes/s)

26system.physmem.bw_read::total 960110 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 480750 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 480750 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 480750 # Total bandwidth to/from this memory (bytes/s)

30system.physmem.bw_total::cpu.data 479360 # Total bandwidth to/from this memory (bytes/s)

31system.physmem.bw_total::total 960111 # Total bandwidth to/from this memory (bytes/s)

31system.physmem.bw_total::total 960110 # Total bandwidth to/from this memory (bytes/s)

32system.cpu_clk_domain.clock 500 # Clock period in ticks
33system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
34system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
35system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
36system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 102 unchanged lines hidden (view full) ---

142system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
143system.cpu.itb.read_accesses 0 # DTB read accesses
144system.cpu.itb.write_accesses 0 # DTB write accesses
145system.cpu.itb.inst_accesses 0 # ITB inst accesses
146system.cpu.itb.hits 0 # DTB hits
147system.cpu.itb.misses 0 # DTB misses
148system.cpu.itb.accesses 0 # DTB accesses
149system.cpu.workload.num_syscalls 400 # Number of system calls

150system.cpu.numCycles 460346717 # number of cpu cycles simulated

150system.cpu.numCycles 460347041 # number of cpu cycles simulated

151system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
152system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
153system.cpu.committedInsts 171842484 # Number of instructions committed
154system.cpu.committedOps 181165371 # Number of ops (including micro ops) committed
155system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses
156system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
157system.cpu.num_func_calls 3545028 # number of times a function call or return occured
158system.cpu.num_conditional_control_insts 32201008 # number of instructions that are conditional controls

--- 4 unchanged lines hidden (view full) ---

163system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read
164system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written
165system.cpu.num_cc_register_reads 626384530 # number of times the CC registers were read
166system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written
167system.cpu.num_mem_refs 40540779 # number of memory refs
168system.cpu.num_load_insts 27896144 # Number of load instructions
169system.cpu.num_store_insts 12644635 # Number of store instructions
170system.cpu.num_idle_cycles 0.002000 # Number of idle cycles

171system.cpu.num_busy_cycles 460346716.998000 # Number of busy cycles

171system.cpu.num_busy_cycles 460347040.998000 # Number of busy cycles

172system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
173system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
174system.cpu.Branches 40300312 # Number of branches fetched
175system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
176system.cpu.op_class::IntAlu 138988213 76.51% 76.51% # Class of executed instruction
177system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction
178system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction
179system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction

--- 23 unchanged lines hidden (view full) ---

203system.cpu.op_class::SimdFloatMultAcc 71617 0.04% 77.68% # Class of executed instruction
204system.cpu.op_class::SimdFloatSqrt 318 0.00% 77.68% # Class of executed instruction
205system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Class of executed instruction
206system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction
207system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
208system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
209system.cpu.op_class::total 181650743 # Class of executed instruction
210system.cpu.dcache.tags.replacements 40 # number of replacements

211system.cpu.dcache.tags.tagsinuse 1363.619267 # Cycle average of tags in use

211system.cpu.dcache.tags.tagsinuse 1363.619059 # Cycle average of tags in use

212system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks.
213system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks.
214system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks.
215system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

216system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619267 # Average occupied blocks per requestor

216system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619059 # Average occupied blocks per requestor

217system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy
218system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy
219system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id
220system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 # Occupied blocks per task id
221system.cpu.dcache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
222system.cpu.dcache.tags.age_task_id_blocks_1024::2 67 # Occupied blocks per task id
223system.cpu.dcache.tags.age_task_id_blocks_1024::3 302 # Occupied blocks per task id
224system.cpu.dcache.tags.age_task_id_blocks_1024::4 1345 # Occupied blocks per task id

--- 19 unchanged lines hidden (view full) ---

244system.cpu.dcache.WriteReq_misses::cpu.data 1100 # number of WriteReq misses
245system.cpu.dcache.WriteReq_misses::total 1100 # number of WriteReq misses
246system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
247system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
248system.cpu.dcache.demand_misses::cpu.data 1788 # number of demand (read+write) misses
249system.cpu.dcache.demand_misses::total 1788 # number of demand (read+write) misses
250system.cpu.dcache.overall_misses::cpu.data 1789 # number of overall misses
251system.cpu.dcache.overall_misses::total 1789 # number of overall misses

252system.cpu.dcache.ReadReq_miss_latency::cpu.data 35469000 # number of ReadReq miss cycles
253system.cpu.dcache.ReadReq_miss_latency::total 35469000 # number of ReadReq miss cycles

252system.cpu.dcache.ReadReq_miss_latency::cpu.data 35518000 # number of ReadReq miss cycles
253system.cpu.dcache.ReadReq_miss_latency::total 35518000 # number of ReadReq miss cycles

254system.cpu.dcache.WriteReq_miss_latency::cpu.data 60194500 # number of WriteReq miss cycles
255system.cpu.dcache.WriteReq_miss_latency::total 60194500 # number of WriteReq miss cycles

256system.cpu.dcache.demand_miss_latency::cpu.data 95663500 # number of demand (read+write) miss cycles
257system.cpu.dcache.demand_miss_latency::total 95663500 # number of demand (read+write) miss cycles
258system.cpu.dcache.overall_miss_latency::cpu.data 95663500 # number of overall miss cycles
259system.cpu.dcache.overall_miss_latency::total 95663500 # number of overall miss cycles

256system.cpu.dcache.demand_miss_latency::cpu.data 95712500 # number of demand (read+write) miss cycles
257system.cpu.dcache.demand_miss_latency::total 95712500 # number of demand (read+write) miss cycles
258system.cpu.dcache.overall_miss_latency::cpu.data 95712500 # number of overall miss cycles
259system.cpu.dcache.overall_miss_latency::total 95712500 # number of overall miss cycles

260system.cpu.dcache.ReadReq_accesses::cpu.data 27754851 # number of ReadReq accesses(hits+misses)
261system.cpu.dcache.ReadReq_accesses::total 27754851 # number of ReadReq accesses(hits+misses)
262system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses)
263system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses)
264system.cpu.dcache.SoftPFReq_accesses::cpu.data 463 # number of SoftPFReq accesses(hits+misses)
265system.cpu.dcache.SoftPFReq_accesses::total 463 # number of SoftPFReq accesses(hits+misses)
266system.cpu.dcache.LoadLockedReq_accesses::cpu.data 22407 # number of LoadLockedReq accesses(hits+misses)
267system.cpu.dcache.LoadLockedReq_accesses::total 22407 # number of LoadLockedReq accesses(hits+misses)

--- 8 unchanged lines hidden (view full) ---

276system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000089 # miss rate for WriteReq accesses
277system.cpu.dcache.WriteReq_miss_rate::total 0.000089 # miss rate for WriteReq accesses
278system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.002160 # miss rate for SoftPFReq accesses
279system.cpu.dcache.SoftPFReq_miss_rate::total 0.002160 # miss rate for SoftPFReq accesses
280system.cpu.dcache.demand_miss_rate::cpu.data 0.000045 # miss rate for demand accesses
281system.cpu.dcache.demand_miss_rate::total 0.000045 # miss rate for demand accesses
282system.cpu.dcache.overall_miss_rate::cpu.data 0.000045 # miss rate for overall accesses
283system.cpu.dcache.overall_miss_rate::total 0.000045 # miss rate for overall accesses

284system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51553.779070 # average ReadReq miss latency
285system.cpu.dcache.ReadReq_avg_miss_latency::total 51553.779070 # average ReadReq miss latency

284system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51625 # average ReadReq miss latency
285system.cpu.dcache.ReadReq_avg_miss_latency::total 51625 # average ReadReq miss latency

286system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54722.272727 # average WriteReq miss latency
287system.cpu.dcache.WriteReq_avg_miss_latency::total 54722.272727 # average WriteReq miss latency

288system.cpu.dcache.demand_avg_miss_latency::cpu.data 53503.076063 # average overall miss latency
289system.cpu.dcache.demand_avg_miss_latency::total 53503.076063 # average overall miss latency
290system.cpu.dcache.overall_avg_miss_latency::cpu.data 53473.169368 # average overall miss latency
291system.cpu.dcache.overall_avg_miss_latency::total 53473.169368 # average overall miss latency

288system.cpu.dcache.demand_avg_miss_latency::cpu.data 53530.480984 # average overall miss latency
289system.cpu.dcache.demand_avg_miss_latency::total 53530.480984 # average overall miss latency
290system.cpu.dcache.overall_avg_miss_latency::cpu.data 53500.558971 # average overall miss latency
291system.cpu.dcache.overall_avg_miss_latency::total 53500.558971 # average overall miss latency

292system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
293system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
294system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
295system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
296system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
297system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
298system.cpu.dcache.fast_writes 0 # number of fast writes performed
299system.cpu.dcache.cache_copies 0 # number of cache copies performed

--- 4 unchanged lines hidden (view full) ---

304system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1100 # number of WriteReq MSHR misses
305system.cpu.dcache.WriteReq_mshr_misses::total 1100 # number of WriteReq MSHR misses
306system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
307system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
308system.cpu.dcache.demand_mshr_misses::cpu.data 1788 # number of demand (read+write) MSHR misses
309system.cpu.dcache.demand_mshr_misses::total 1788 # number of demand (read+write) MSHR misses
310system.cpu.dcache.overall_mshr_misses::cpu.data 1789 # number of overall MSHR misses
311system.cpu.dcache.overall_mshr_misses::total 1789 # number of overall MSHR misses

312system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34781000 # number of ReadReq MSHR miss cycles
313system.cpu.dcache.ReadReq_mshr_miss_latency::total 34781000 # number of ReadReq MSHR miss cycles

312system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34830000 # number of ReadReq MSHR miss cycles
313system.cpu.dcache.ReadReq_mshr_miss_latency::total 34830000 # number of ReadReq MSHR miss cycles

314system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 59094500 # number of WriteReq MSHR miss cycles
315system.cpu.dcache.WriteReq_mshr_miss_latency::total 59094500 # number of WriteReq MSHR miss cycles
316system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 54000 # number of SoftPFReq MSHR miss cycles
317system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 54000 # number of SoftPFReq MSHR miss cycles

318system.cpu.dcache.demand_mshr_miss_latency::cpu.data 93875500 # number of demand (read+write) MSHR miss cycles
319system.cpu.dcache.demand_mshr_miss_latency::total 93875500 # number of demand (read+write) MSHR miss cycles
320system.cpu.dcache.overall_mshr_miss_latency::cpu.data 93929500 # number of overall MSHR miss cycles
321system.cpu.dcache.overall_mshr_miss_latency::total 93929500 # number of overall MSHR miss cycles

318system.cpu.dcache.demand_mshr_miss_latency::cpu.data 93924500 # number of demand (read+write) MSHR miss cycles
319system.cpu.dcache.demand_mshr_miss_latency::total 93924500 # number of demand (read+write) MSHR miss cycles
320system.cpu.dcache.overall_mshr_miss_latency::cpu.data 93978500 # number of overall MSHR miss cycles
321system.cpu.dcache.overall_mshr_miss_latency::total 93978500 # number of overall MSHR miss cycles

322system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for ReadReq accesses
323system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000025 # mshr miss rate for ReadReq accesses
324system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000089 # mshr miss rate for WriteReq accesses
325system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000089 # mshr miss rate for WriteReq accesses
326system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.002160 # mshr miss rate for SoftPFReq accesses
327system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.002160 # mshr miss rate for SoftPFReq accesses
328system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for demand accesses
329system.cpu.dcache.demand_mshr_miss_rate::total 0.000045 # mshr miss rate for demand accesses
330system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000045 # mshr miss rate for overall accesses
331system.cpu.dcache.overall_mshr_miss_rate::total 0.000045 # mshr miss rate for overall accesses

332system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50553.779070 # average ReadReq mshr miss latency
333system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50553.779070 # average ReadReq mshr miss latency

332system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50625 # average ReadReq mshr miss latency
333system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50625 # average ReadReq mshr miss latency

334system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53722.272727 # average WriteReq mshr miss latency
335system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53722.272727 # average WriteReq mshr miss latency
336system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 54000 # average SoftPFReq mshr miss latency
337system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 54000 # average SoftPFReq mshr miss latency

338system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52503.076063 # average overall mshr miss latency
339system.cpu.dcache.demand_avg_mshr_miss_latency::total 52503.076063 # average overall mshr miss latency
340system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52503.912800 # average overall mshr miss latency
341system.cpu.dcache.overall_avg_mshr_miss_latency::total 52503.912800 # average overall mshr miss latency

338system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52530.480984 # average overall mshr miss latency
339system.cpu.dcache.demand_avg_mshr_miss_latency::total 52530.480984 # average overall mshr miss latency
340system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52531.302404 # average overall mshr miss latency
341system.cpu.dcache.overall_avg_mshr_miss_latency::total 52531.302404 # average overall mshr miss latency

342system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
343system.cpu.icache.tags.replacements 1506 # number of replacements

344system.cpu.icache.tags.tagsinuse 1147.992590 # Cycle average of tags in use

344system.cpu.icache.tags.tagsinuse 1147.992416 # Cycle average of tags in use

345system.cpu.icache.tags.total_refs 189857002 # Total number of references to valid blocks.
346system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks.
347system.cpu.icache.tags.avg_refs 62227.794821 # Average number of references to valid blocks.
348system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

349system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992590 # Average occupied blocks per requestor

349system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992416 # Average occupied blocks per requestor

350system.cpu.icache.tags.occ_percent::cpu.inst 0.560543 # Average percentage of cache occupancy
351system.cpu.icache.tags.occ_percent::total 0.560543 # Average percentage of cache occupancy
352system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id
353system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
354system.cpu.icache.tags.age_task_id_blocks_1024::1 21 # Occupied blocks per task id
355system.cpu.icache.tags.age_task_id_blocks_1024::2 288 # Occupied blocks per task id
356system.cpu.icache.tags.age_task_id_blocks_1024::3 270 # Occupied blocks per task id
357system.cpu.icache.tags.age_task_id_blocks_1024::4 942 # Occupied blocks per task id

--- 7 unchanged lines hidden (view full) ---

365system.cpu.icache.overall_hits::cpu.inst 189857002 # number of overall hits
366system.cpu.icache.overall_hits::total 189857002 # number of overall hits
367system.cpu.icache.ReadReq_misses::cpu.inst 3051 # number of ReadReq misses
368system.cpu.icache.ReadReq_misses::total 3051 # number of ReadReq misses
369system.cpu.icache.demand_misses::cpu.inst 3051 # number of demand (read+write) misses
370system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses
371system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses
372system.cpu.icache.overall_misses::total 3051 # number of overall misses

373system.cpu.icache.ReadReq_miss_latency::cpu.inst 112371000 # number of ReadReq miss cycles
374system.cpu.icache.ReadReq_miss_latency::total 112371000 # number of ReadReq miss cycles
375system.cpu.icache.demand_miss_latency::cpu.inst 112371000 # number of demand (read+write) miss cycles
376system.cpu.icache.demand_miss_latency::total 112371000 # number of demand (read+write) miss cycles
377system.cpu.icache.overall_miss_latency::cpu.inst 112371000 # number of overall miss cycles
378system.cpu.icache.overall_miss_latency::total 112371000 # number of overall miss cycles

373system.cpu.icache.ReadReq_miss_latency::cpu.inst 112484000 # number of ReadReq miss cycles
374system.cpu.icache.ReadReq_miss_latency::total 112484000 # number of ReadReq miss cycles
375system.cpu.icache.demand_miss_latency::cpu.inst 112484000 # number of demand (read+write) miss cycles
376system.cpu.icache.demand_miss_latency::total 112484000 # number of demand (read+write) miss cycles
377system.cpu.icache.overall_miss_latency::cpu.inst 112484000 # number of overall miss cycles
378system.cpu.icache.overall_miss_latency::total 112484000 # number of overall miss cycles

379system.cpu.icache.ReadReq_accesses::cpu.inst 189860053 # number of ReadReq accesses(hits+misses)
380system.cpu.icache.ReadReq_accesses::total 189860053 # number of ReadReq accesses(hits+misses)
381system.cpu.icache.demand_accesses::cpu.inst 189860053 # number of demand (read+write) accesses
382system.cpu.icache.demand_accesses::total 189860053 # number of demand (read+write) accesses
383system.cpu.icache.overall_accesses::cpu.inst 189860053 # number of overall (read+write) accesses
384system.cpu.icache.overall_accesses::total 189860053 # number of overall (read+write) accesses
385system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses
386system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses
387system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses
388system.cpu.icache.demand_miss_rate::total 0.000016 # miss rate for demand accesses
389system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
390system.cpu.icache.overall_miss_rate::total 0.000016 # miss rate for overall accesses

391system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36830.875123 # average ReadReq miss latency
392system.cpu.icache.ReadReq_avg_miss_latency::total 36830.875123 # average ReadReq miss latency
393system.cpu.icache.demand_avg_miss_latency::cpu.inst 36830.875123 # average overall miss latency
394system.cpu.icache.demand_avg_miss_latency::total 36830.875123 # average overall miss latency
395system.cpu.icache.overall_avg_miss_latency::cpu.inst 36830.875123 # average overall miss latency
396system.cpu.icache.overall_avg_miss_latency::total 36830.875123 # average overall miss latency

391system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36867.912160 # average ReadReq miss latency
392system.cpu.icache.ReadReq_avg_miss_latency::total 36867.912160 # average ReadReq miss latency
393system.cpu.icache.demand_avg_miss_latency::cpu.inst 36867.912160 # average overall miss latency
394system.cpu.icache.demand_avg_miss_latency::total 36867.912160 # average overall miss latency
395system.cpu.icache.overall_avg_miss_latency::cpu.inst 36867.912160 # average overall miss latency
396system.cpu.icache.overall_avg_miss_latency::total 36867.912160 # average overall miss latency

397system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
398system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
399system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
400system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
401system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
402system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
403system.cpu.icache.fast_writes 0 # number of fast writes performed
404system.cpu.icache.cache_copies 0 # number of cache copies performed
405system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3051 # number of ReadReq MSHR misses
406system.cpu.icache.ReadReq_mshr_misses::total 3051 # number of ReadReq MSHR misses
407system.cpu.icache.demand_mshr_misses::cpu.inst 3051 # number of demand (read+write) MSHR misses
408system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses
409system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses
410system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses

411system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 109320000 # number of ReadReq MSHR miss cycles
412system.cpu.icache.ReadReq_mshr_miss_latency::total 109320000 # number of ReadReq MSHR miss cycles
413system.cpu.icache.demand_mshr_miss_latency::cpu.inst 109320000 # number of demand (read+write) MSHR miss cycles
414system.cpu.icache.demand_mshr_miss_latency::total 109320000 # number of demand (read+write) MSHR miss cycles
415system.cpu.icache.overall_mshr_miss_latency::cpu.inst 109320000 # number of overall MSHR miss cycles
416system.cpu.icache.overall_mshr_miss_latency::total 109320000 # number of overall MSHR miss cycles

411system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 109433000 # number of ReadReq MSHR miss cycles
412system.cpu.icache.ReadReq_mshr_miss_latency::total 109433000 # number of ReadReq MSHR miss cycles
413system.cpu.icache.demand_mshr_miss_latency::cpu.inst 109433000 # number of demand (read+write) MSHR miss cycles
414system.cpu.icache.demand_mshr_miss_latency::total 109433000 # number of demand (read+write) MSHR miss cycles
415system.cpu.icache.overall_mshr_miss_latency::cpu.inst 109433000 # number of overall MSHR miss cycles
416system.cpu.icache.overall_mshr_miss_latency::total 109433000 # number of overall MSHR miss cycles

417system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses
418system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000016 # mshr miss rate for ReadReq accesses
419system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses
420system.cpu.icache.demand_mshr_miss_rate::total 0.000016 # mshr miss rate for demand accesses
421system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for overall accesses
422system.cpu.icache.overall_mshr_miss_rate::total 0.000016 # mshr miss rate for overall accesses

423system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35830.875123 # average ReadReq mshr miss latency
424system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35830.875123 # average ReadReq mshr miss latency
425system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35830.875123 # average overall mshr miss latency
426system.cpu.icache.demand_avg_mshr_miss_latency::total 35830.875123 # average overall mshr miss latency
427system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35830.875123 # average overall mshr miss latency
428system.cpu.icache.overall_avg_mshr_miss_latency::total 35830.875123 # average overall mshr miss latency

423system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35867.912160 # average ReadReq mshr miss latency
424system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35867.912160 # average ReadReq mshr miss latency
425system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35867.912160 # average overall mshr miss latency
426system.cpu.icache.demand_avg_mshr_miss_latency::total 35867.912160 # average overall mshr miss latency
427system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35867.912160 # average overall mshr miss latency
428system.cpu.icache.overall_avg_mshr_miss_latency::total 35867.912160 # average overall mshr miss latency

429system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
430system.cpu.l2cache.tags.replacements 0 # number of replacements

431system.cpu.l2cache.tags.tagsinuse 1675.663321 # Cycle average of tags in use

431system.cpu.l2cache.tags.tagsinuse 1675.663068 # Cycle average of tags in use

432system.cpu.l2cache.tags.total_refs 2846 # Total number of references to valid blocks.
433system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks.
434system.cpu.l2cache.tags.avg_refs 1.201351 # Average number of references to valid blocks.
435system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
436system.cpu.l2cache.tags.occ_blocks::writebacks 3.037779 # Average occupied blocks per requestor

437system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036732 # Average occupied blocks per requestor
438system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588811 # Average occupied blocks per requestor

437system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036560 # Average occupied blocks per requestor
438system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588729 # Average occupied blocks per requestor

439system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy
440system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy
441system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy
442system.cpu.l2cache.tags.occ_percent::total 0.051137 # Average percentage of cache occupancy
443system.cpu.l2cache.tags.occ_task_id_blocks::1024 2369 # Occupied blocks per task id
444system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
445system.cpu.l2cache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
446system.cpu.l2cache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id

--- 130 unchanged lines hidden (view full) ---

577system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42536.392405 # average ReadSharedReq mshr miss latency
578system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42552.053210 # average overall mshr miss latency
579system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42531.032483 # average overall mshr miss latency
580system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42541.558065 # average overall mshr miss latency
581system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42552.053210 # average overall mshr miss latency
582system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42531.032483 # average overall mshr miss latency
583system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42541.558065 # average overall mshr miss latency
584system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

585system.cpu.toL2Bus.snoop_filter.tot_requests 6386 # Total number of requests made to the snoop filter.
586system.cpu.toL2Bus.snoop_filter.hit_single_requests 1644 # Number of requests hitting in the snoop filter with a single holder of the requested data.
587system.cpu.toL2Bus.snoop_filter.hit_multi_requests 64 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
588system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
589system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
590system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

585system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution
586system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution
587system.cpu.toL2Bus.trans_dist::CleanEvict 1466 # Transaction distribution
588system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution
589system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution
590system.cpu.toL2Bus.trans_dist::ReadCleanReq 3051 # Transaction distribution
591system.cpu.toL2Bus.trans_dist::ReadSharedReq 689 # Transaction distribution
592system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7550 # Packet count per connected master and slave (bytes)
593system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3612 # Packet count per connected master and slave (bytes)
594system.cpu.toL2Bus.pkt_count::total 11162 # Packet count per connected master and slave (bytes)
595system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 195264 # Cumulative packet size per connected master and slave (bytes)
596system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes)
597system.cpu.toL2Bus.pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes)
598system.cpu.toL2Bus.snoops 0 # Total snoops (count)
599system.cpu.toL2Bus.snoop_fanout::samples 6386 # Request fanout histogram

591system.cpu.toL2Bus.trans_dist::ReadResp 3740 # Transaction distribution
592system.cpu.toL2Bus.trans_dist::Writeback 16 # Transaction distribution
593system.cpu.toL2Bus.trans_dist::CleanEvict 1466 # Transaction distribution
594system.cpu.toL2Bus.trans_dist::ReadExReq 1100 # Transaction distribution
595system.cpu.toL2Bus.trans_dist::ReadExResp 1100 # Transaction distribution
596system.cpu.toL2Bus.trans_dist::ReadCleanReq 3051 # Transaction distribution
597system.cpu.toL2Bus.trans_dist::ReadSharedReq 689 # Transaction distribution
598system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7550 # Packet count per connected master and slave (bytes)
599system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 3612 # Packet count per connected master and slave (bytes)
600system.cpu.toL2Bus.pkt_count::total 11162 # Packet count per connected master and slave (bytes)
601system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 195264 # Cumulative packet size per connected master and slave (bytes)
602system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 115520 # Cumulative packet size per connected master and slave (bytes)
603system.cpu.toL2Bus.pkt_size::total 310784 # Cumulative packet size per connected master and slave (bytes)
604system.cpu.toL2Bus.snoops 0 # Total snoops (count)
605system.cpu.toL2Bus.snoop_fanout::samples 6386 # Request fanout histogram

600system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
601system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram

606system.cpu.toL2Bus.snoop_fanout::mean 0.035390 # Request fanout histogram
607system.cpu.toL2Bus.snoop_fanout::stdev 0.184778 # Request fanout histogram

602system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

608system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

603system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
604system.cpu.toL2Bus.snoop_fanout::1 6386 100.00% 100.00% # Request fanout histogram

609system.cpu.toL2Bus.snoop_fanout::0 6160 96.46% 96.46% # Request fanout histogram
610system.cpu.toL2Bus.snoop_fanout::1 226 3.54% 100.00% # Request fanout histogram

605system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
606system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

611system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
612system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

607system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram

613system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram