3,5c3,5
< sim_seconds 0.230198 # Number of seconds simulated
< sim_ticks 230197694500 # Number of ticks simulated
< final_tick 230197694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.230201 # Number of seconds simulated
> sim_ticks 230201146500 # Number of ticks simulated
> final_tick 230201146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 688414 # Simulator instruction rate (inst/s)
< host_op_rate 725763 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 922189750 # Simulator tick rate (ticks/s)
< host_mem_usage 268612 # Number of bytes of host memory used
< host_seconds 249.62 # Real time elapsed on the host
---
> host_inst_rate 826360 # Simulator instruction rate (inst/s)
> host_op_rate 871192 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1106995865 # Simulator tick rate (ticks/s)
> host_mem_usage 273252 # Number of bytes of host memory used
> host_seconds 207.95 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states
25,33c25,33
< system.physmem.bw_read::cpu.inst 480700 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 479310 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 960010 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 480700 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 480700 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 480700 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 479310 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 960010 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
---
> system.physmem.bw_read::cpu.inst 480693 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 479303 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 959995 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 480693 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 480693 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 480693 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 479303 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 959995 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states
35c35
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states
65c65
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states
95c95
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states
125c125
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states
156,157c156,157
< system.cpu.pwrStateResidencyTicks::ON 230197694500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 460395389 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 230201146500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 460402293 # number of cpu cycles simulated
178c178
< system.cpu.num_busy_cycles 460395388.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 460402292.998000 # Number of busy cycles
217c217
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states
219c219
< system.cpu.dcache.tags.tagsinuse 1363.571253 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 1363.564425 # Cycle average of tags in use
224,226c224,226
< system.cpu.dcache.tags.occ_blocks::cpu.data 1363.571253 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.332903 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.332903 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 1363.564425 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.332901 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.332901 # Average percentage of cache occupancy
236c236
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states
261,268c261,268
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 39940000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 39940000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 67838500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 67838500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 107778500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 107778500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 107778500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 107778500 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 40571000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 40571000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 68930500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 68930500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 109501500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 109501500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 109501500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 109501500 # number of overall miss cycles
293,300c293,300
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58052.325581 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 58052.325581 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61671.363636 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 61671.363636 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 60278.803132 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 60278.803132 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 60245.108999 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 60245.108999 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58969.476744 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 58969.476744 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62664.090909 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 62664.090909 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 61242.449664 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 61242.449664 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 61208.216881 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 61208.216881 # average overall miss latency
319,328c319,328
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39252000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 39252000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 66738500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 66738500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 105990500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 105990500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 106051500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 106051500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39883000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 39883000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67830500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 67830500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 107713500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 107713500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 107775500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 107775500 # number of overall MSHR miss cycles
339,349c339,349
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57052.325581 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57052.325581 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60671.363636 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60671.363636 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59278.803132 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 59278.803132 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59279.765232 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 59279.765232 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57969.476744 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57969.476744 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61664.090909 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61664.090909 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60242.449664 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 60242.449664 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60243.432085 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 60243.432085 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states
351c351
< system.cpu.icache.tags.tagsinuse 1147.958164 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1147.953271 # Cycle average of tags in use
356,358c356,358
< system.cpu.icache.tags.occ_blocks::cpu.inst 1147.958164 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.560526 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.560526 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1147.953271 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.560524 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.560524 # Average percentage of cache occupancy
368c368
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states
381,386c381,386
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 124592000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 124592000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 124592000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 124592000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 124592000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 124592000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 126321000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 126321000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 126321000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 126321000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 126321000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 126321000 # number of overall miss cycles
399,404c399,404
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40836.447067 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 40836.447067 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 40836.447067 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 40836.447067 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 40836.447067 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 40836.447067 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41403.146509 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 41403.146509 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 41403.146509 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 41403.146509 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 41403.146509 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 41403.146509 # average overall miss latency
419,424c419,424
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 121541000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 121541000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 121541000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 121541000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 121541000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 121541000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 123270000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 123270000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 123270000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 123270000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 123270000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 123270000 # number of overall MSHR miss cycles
431,437c431,437
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39836.447067 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39836.447067 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40403.146509 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40403.146509 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40403.146509 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 40403.146509 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40403.146509 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 40403.146509 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states
439,442c439,442
< system.cpu.l2cache.tags.tagsinuse 1675.610098 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2846 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 1.201351 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 2511.620011 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2869 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 3453 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.830872 # Average number of references to valid blocks.
444,447c444,445
< system.cpu.l2cache.tags.occ_blocks::writebacks 3.037805 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.001518 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 503.570775 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 1168.996513 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 1342.623498 # Average occupied blocks per requestor
449,460c447,458
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.051136 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 2369 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 322 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1679 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.072296 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 54045 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 54045 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.040974 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.076649 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 3453 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 536 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2517 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.105377 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 54029 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 54029 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states
489,500c487,498
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 65004500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 65004500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 102968000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 102968000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 37629500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 37629500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 102968000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 102634000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 205602000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 102968000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 102634000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 205602000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66096500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 66096500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 104697000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 104697000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 38261500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 38261500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 104697000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 104358000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 209055000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 104697000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 104358000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 209055000 # number of overall miss cycles
529,540c527,538
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59527.930403 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59527.930403 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59553.499132 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59553.499132 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59540.348101 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59540.348101 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59553.499132 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59532.482599 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59543.006082 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59553.499132 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59532.482599 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59543.006082 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60527.930403 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60527.930403 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60553.499132 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60553.499132 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60540.348101 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60540.348101 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60553.499132 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60532.482599 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60543.006082 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60553.499132 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60532.482599 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60543.006082 # average overall miss latency
559,570c557,568
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54084500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54084500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85678000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85678000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31309500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31309500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85678000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85394000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 171072000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85678000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85394000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 171072000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 55176500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 55176500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 87407000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 87407000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31941500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31941500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87407000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87118000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 174525000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87407000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87118000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 174525000 # number of overall MSHR miss cycles
583,594c581,592
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49527.930403 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49527.930403 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49553.499132 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49553.499132 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49540.348101 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49540.348101 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49553.499132 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49532.482599 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49543.006082 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49553.499132 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49532.482599 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49543.006082 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50527.930403 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50527.930403 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50553.499132 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50553.499132 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50540.348101 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50540.348101 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50553.499132 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50532.482599 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50543.006082 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50553.499132 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50532.482599 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50543.006082 # average overall mshr miss latency
601c599
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states
635c633,639
< system.membus.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 3453 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states
< sim_seconds 0.230198 # Number of seconds simulated
< sim_ticks 230197694500 # Number of ticks simulated
< final_tick 230197694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.230201 # Number of seconds simulated
> sim_ticks 230201146500 # Number of ticks simulated
> final_tick 230201146500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 688414 # Simulator instruction rate (inst/s)
< host_op_rate 725763 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 922189750 # Simulator tick rate (ticks/s)
< host_mem_usage 268612 # Number of bytes of host memory used
< host_seconds 249.62 # Real time elapsed on the host
---
> host_inst_rate 826360 # Simulator instruction rate (inst/s)
> host_op_rate 871192 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1106995865 # Simulator tick rate (ticks/s)
> host_mem_usage 273252 # Number of bytes of host memory used
> host_seconds 207.95 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states
25,33c25,33
< system.physmem.bw_read::cpu.inst 480700 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 479310 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 960010 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 480700 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 480700 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 480700 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 479310 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 960010 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
---
> system.physmem.bw_read::cpu.inst 480693 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 479303 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 959995 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 480693 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 480693 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 480693 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 479303 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 959995 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states
35c35
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states
65c65
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states
95c95
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states
125c125
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states
156,157c156,157
< system.cpu.pwrStateResidencyTicks::ON 230197694500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 460395389 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 230201146500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 460402293 # number of cpu cycles simulated
178c178
< system.cpu.num_busy_cycles 460395388.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 460402292.998000 # Number of busy cycles
217c217
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states
219c219
< system.cpu.dcache.tags.tagsinuse 1363.571253 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 1363.564425 # Cycle average of tags in use
224,226c224,226
< system.cpu.dcache.tags.occ_blocks::cpu.data 1363.571253 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.332903 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.332903 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 1363.564425 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.332901 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.332901 # Average percentage of cache occupancy
236c236
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states
261,268c261,268
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 39940000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 39940000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 67838500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 67838500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 107778500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 107778500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 107778500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 107778500 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 40571000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 40571000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 68930500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 68930500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 109501500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 109501500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 109501500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 109501500 # number of overall miss cycles
293,300c293,300
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58052.325581 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 58052.325581 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61671.363636 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 61671.363636 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 60278.803132 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 60278.803132 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 60245.108999 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 60245.108999 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58969.476744 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 58969.476744 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62664.090909 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 62664.090909 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 61242.449664 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 61242.449664 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 61208.216881 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 61208.216881 # average overall miss latency
319,328c319,328
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39252000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 39252000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 66738500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 66738500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 61000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 61000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 105990500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 105990500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 106051500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 106051500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 39883000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 39883000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 67830500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 67830500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 107713500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 107713500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 107775500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 107775500 # number of overall MSHR miss cycles
339,349c339,349
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57052.325581 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57052.325581 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60671.363636 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60671.363636 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 61000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 61000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59278.803132 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 59278.803132 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59279.765232 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 59279.765232 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57969.476744 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57969.476744 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61664.090909 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61664.090909 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 60242.449664 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 60242.449664 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 60243.432085 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 60243.432085 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states
351c351
< system.cpu.icache.tags.tagsinuse 1147.958164 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1147.953271 # Cycle average of tags in use
356,358c356,358
< system.cpu.icache.tags.occ_blocks::cpu.inst 1147.958164 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.560526 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.560526 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1147.953271 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.560524 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.560524 # Average percentage of cache occupancy
368c368
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states
381,386c381,386
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 124592000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 124592000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 124592000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 124592000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 124592000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 124592000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 126321000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 126321000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 126321000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 126321000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 126321000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 126321000 # number of overall miss cycles
399,404c399,404
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 40836.447067 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 40836.447067 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 40836.447067 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 40836.447067 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 40836.447067 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 40836.447067 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 41403.146509 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 41403.146509 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 41403.146509 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 41403.146509 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 41403.146509 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 41403.146509 # average overall miss latency
419,424c419,424
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 121541000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 121541000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 121541000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 121541000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 121541000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 121541000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 123270000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 123270000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 123270000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 123270000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 123270000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 123270000 # number of overall MSHR miss cycles
431,437c431,437
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 39836.447067 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 39836.447067 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 39836.447067 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 39836.447067 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 40403.146509 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 40403.146509 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 40403.146509 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 40403.146509 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 40403.146509 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 40403.146509 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states
439,442c439,442
< system.cpu.l2cache.tags.tagsinuse 1675.610098 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 2846 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 1.201351 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.tagsinuse 2511.620011 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 2869 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 3453 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.830872 # Average number of references to valid blocks.
444,447c444,445
< system.cpu.l2cache.tags.occ_blocks::writebacks 3.037805 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.001518 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 503.570775 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 1168.996513 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 1342.623498 # Average occupied blocks per requestor
449,460c447,458
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.051136 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 2369 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 18 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 320 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 322 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1679 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.072296 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 54045 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 54045 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.040974 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.076649 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 3453 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 341 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 536 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2517 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.105377 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 54029 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 54029 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states
489,500c487,498
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 65004500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 65004500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 102968000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 102968000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 37629500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 37629500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 102968000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 102634000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 205602000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 102968000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 102634000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 205602000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 66096500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 66096500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 104697000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 104697000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 38261500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 38261500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 104697000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 104358000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 209055000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 104697000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 104358000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 209055000 # number of overall miss cycles
529,540c527,538
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59527.930403 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59527.930403 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59553.499132 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59553.499132 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59540.348101 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59540.348101 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59553.499132 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59532.482599 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59543.006082 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59553.499132 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59532.482599 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59543.006082 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60527.930403 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60527.930403 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60553.499132 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60553.499132 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60540.348101 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60540.348101 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60553.499132 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60532.482599 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60543.006082 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60553.499132 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60532.482599 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60543.006082 # average overall miss latency
559,570c557,568
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54084500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54084500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 85678000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 85678000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31309500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31309500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 85678000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 85394000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 171072000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 85678000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 85394000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 171072000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 55176500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 55176500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 87407000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 87407000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 31941500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 31941500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 87407000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87118000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 174525000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 87407000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87118000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 174525000 # number of overall MSHR miss cycles
583,594c581,592
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49527.930403 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49527.930403 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49553.499132 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49553.499132 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49540.348101 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49540.348101 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49553.499132 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49532.482599 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49543.006082 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49553.499132 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49532.482599 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49543.006082 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50527.930403 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50527.930403 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50553.499132 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50553.499132 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50540.348101 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50540.348101 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50553.499132 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50532.482599 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50543.006082 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50553.499132 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50532.482599 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50543.006082 # average overall mshr miss latency
601c599
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states
635c633,639
< system.membus.pwrStateResidencyTicks::UNDEFINED 230197694500 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 3453 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 230201146500 # Cumulative time (in ticks) in various power states