3,5c3,5
< sim_seconds 0.230173 # Number of seconds simulated
< sim_ticks 230173358500 # Number of ticks simulated
< final_tick 230173358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.230174 # Number of seconds simulated
> sim_ticks 230173520500 # Number of ticks simulated
> final_tick 230173520500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 1194511 # Simulator instruction rate (inst/s)
< host_op_rate 1259316 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1599980237 # Simulator tick rate (ticks/s)
< host_mem_usage 316228 # Number of bytes of host memory used
< host_seconds 143.86 # Real time elapsed on the host
---
> host_inst_rate 1035845 # Simulator instruction rate (inst/s)
> host_op_rate 1092042 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1387457275 # Simulator tick rate (ticks/s)
> host_mem_usage 319880 # Number of bytes of host memory used
> host_seconds 165.90 # Real time elapsed on the host
24c24
< system.physmem.bw_read::cpu.inst 480751 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 480750 # Total read bandwidth from this memory (bytes/s)
26,29c26,29
< system.physmem.bw_read::total 960111 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 480751 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 480751 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 480751 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::total 960110 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 480750 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 480750 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 480750 # Total bandwidth to/from this memory (bytes/s)
31c31
< system.physmem.bw_total::total 960111 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::total 960110 # Total bandwidth to/from this memory (bytes/s)
150c150
< system.cpu.numCycles 460346717 # number of cpu cycles simulated
---
> system.cpu.numCycles 460347041 # number of cpu cycles simulated
171c171
< system.cpu.num_busy_cycles 460346716.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 460347040.998000 # Number of busy cycles
211c211
< system.cpu.dcache.tags.tagsinuse 1363.619267 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 1363.619059 # Cycle average of tags in use
216c216
< system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619267 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619059 # Average occupied blocks per requestor
252,253c252,253
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 35469000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 35469000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 35518000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 35518000 # number of ReadReq miss cycles
256,259c256,259
< system.cpu.dcache.demand_miss_latency::cpu.data 95663500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 95663500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 95663500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 95663500 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 95712500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 95712500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 95712500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 95712500 # number of overall miss cycles
284,285c284,285
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51553.779070 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 51553.779070 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51625 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 51625 # average ReadReq miss latency
288,291c288,291
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 53503.076063 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 53503.076063 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 53473.169368 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 53473.169368 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 53530.480984 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 53530.480984 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 53500.558971 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 53500.558971 # average overall miss latency
312,313c312,313
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34781000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 34781000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34830000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 34830000 # number of ReadReq MSHR miss cycles
318,321c318,321
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 93875500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 93875500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 93929500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 93929500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 93924500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 93924500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 93978500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 93978500 # number of overall MSHR miss cycles
332,333c332,333
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50553.779070 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50553.779070 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50625 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50625 # average ReadReq mshr miss latency
338,341c338,341
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52503.076063 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 52503.076063 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52503.912800 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 52503.912800 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52530.480984 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 52530.480984 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52531.302404 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 52531.302404 # average overall mshr miss latency
344c344
< system.cpu.icache.tags.tagsinuse 1147.992590 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1147.992416 # Cycle average of tags in use
349c349
< system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992590 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992416 # Average occupied blocks per requestor
373,378c373,378
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 112371000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 112371000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 112371000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 112371000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 112371000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 112371000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 112484000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 112484000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 112484000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 112484000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 112484000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 112484000 # number of overall miss cycles
391,396c391,396
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36830.875123 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 36830.875123 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 36830.875123 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 36830.875123 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 36830.875123 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 36830.875123 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36867.912160 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 36867.912160 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 36867.912160 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 36867.912160 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 36867.912160 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 36867.912160 # average overall miss latency
411,416c411,416
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 109320000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 109320000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 109320000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 109320000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 109320000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 109320000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 109433000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 109433000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 109433000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 109433000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 109433000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 109433000 # number of overall MSHR miss cycles
423,428c423,428
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35830.875123 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35830.875123 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35830.875123 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 35830.875123 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35830.875123 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 35830.875123 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35867.912160 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35867.912160 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35867.912160 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 35867.912160 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35867.912160 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 35867.912160 # average overall mshr miss latency
431c431
< system.cpu.l2cache.tags.tagsinuse 1675.663321 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 1675.663068 # Cycle average of tags in use
437,438c437,438
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036732 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588811 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036560 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588729 # Average occupied blocks per requestor
584a585,590
> system.cpu.toL2Bus.snoop_filter.tot_requests 6386 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 1644 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 64 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
600,601c606,607
< system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.035390 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.184778 # Request fanout histogram
603,604c609,610
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 6386 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 6160 96.46% 96.46% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 226 3.54% 100.00% # Request fanout histogram
607c613
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
< sim_seconds 0.230173 # Number of seconds simulated
< sim_ticks 230173358500 # Number of ticks simulated
< final_tick 230173358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.230174 # Number of seconds simulated
> sim_ticks 230173520500 # Number of ticks simulated
> final_tick 230173520500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 1194511 # Simulator instruction rate (inst/s)
< host_op_rate 1259316 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1599980237 # Simulator tick rate (ticks/s)
< host_mem_usage 316228 # Number of bytes of host memory used
< host_seconds 143.86 # Real time elapsed on the host
---
> host_inst_rate 1035845 # Simulator instruction rate (inst/s)
> host_op_rate 1092042 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1387457275 # Simulator tick rate (ticks/s)
> host_mem_usage 319880 # Number of bytes of host memory used
> host_seconds 165.90 # Real time elapsed on the host
24c24
< system.physmem.bw_read::cpu.inst 480751 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 480750 # Total read bandwidth from this memory (bytes/s)
26,29c26,29
< system.physmem.bw_read::total 960111 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 480751 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 480751 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 480751 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::total 960110 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 480750 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 480750 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 480750 # Total bandwidth to/from this memory (bytes/s)
31c31
< system.physmem.bw_total::total 960111 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::total 960110 # Total bandwidth to/from this memory (bytes/s)
150c150
< system.cpu.numCycles 460346717 # number of cpu cycles simulated
---
> system.cpu.numCycles 460347041 # number of cpu cycles simulated
171c171
< system.cpu.num_busy_cycles 460346716.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 460347040.998000 # Number of busy cycles
211c211
< system.cpu.dcache.tags.tagsinuse 1363.619267 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 1363.619059 # Cycle average of tags in use
216c216
< system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619267 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619059 # Average occupied blocks per requestor
252,253c252,253
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 35469000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 35469000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 35518000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 35518000 # number of ReadReq miss cycles
256,259c256,259
< system.cpu.dcache.demand_miss_latency::cpu.data 95663500 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 95663500 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 95663500 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 95663500 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 95712500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 95712500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 95712500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 95712500 # number of overall miss cycles
284,285c284,285
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51553.779070 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 51553.779070 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51625 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 51625 # average ReadReq miss latency
288,291c288,291
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 53503.076063 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 53503.076063 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 53473.169368 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 53473.169368 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 53530.480984 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 53530.480984 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 53500.558971 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 53500.558971 # average overall miss latency
312,313c312,313
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34781000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 34781000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 34830000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 34830000 # number of ReadReq MSHR miss cycles
318,321c318,321
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 93875500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 93875500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 93929500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 93929500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 93924500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 93924500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 93978500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 93978500 # number of overall MSHR miss cycles
332,333c332,333
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50553.779070 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50553.779070 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 50625 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 50625 # average ReadReq mshr miss latency
338,341c338,341
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52503.076063 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 52503.076063 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52503.912800 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 52503.912800 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52530.480984 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 52530.480984 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52531.302404 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 52531.302404 # average overall mshr miss latency
344c344
< system.cpu.icache.tags.tagsinuse 1147.992590 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 1147.992416 # Cycle average of tags in use
349c349
< system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992590 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992416 # Average occupied blocks per requestor
373,378c373,378
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 112371000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 112371000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 112371000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 112371000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 112371000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 112371000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 112484000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 112484000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 112484000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 112484000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 112484000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 112484000 # number of overall miss cycles
391,396c391,396
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36830.875123 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 36830.875123 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 36830.875123 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 36830.875123 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 36830.875123 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 36830.875123 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36867.912160 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 36867.912160 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 36867.912160 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 36867.912160 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 36867.912160 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 36867.912160 # average overall miss latency
411,416c411,416
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 109320000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 109320000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 109320000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 109320000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 109320000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 109320000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 109433000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 109433000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 109433000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 109433000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 109433000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 109433000 # number of overall MSHR miss cycles
423,428c423,428
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35830.875123 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35830.875123 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35830.875123 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 35830.875123 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35830.875123 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 35830.875123 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35867.912160 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35867.912160 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35867.912160 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 35867.912160 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35867.912160 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 35867.912160 # average overall mshr miss latency
431c431
< system.cpu.l2cache.tags.tagsinuse 1675.663321 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 1675.663068 # Cycle average of tags in use
437,438c437,438
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036732 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588811 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036560 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588729 # Average occupied blocks per requestor
584a585,590
> system.cpu.toL2Bus.snoop_filter.tot_requests 6386 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 1644 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 64 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
600,601c606,607
< system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.035390 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.184778 # Request fanout histogram
603,604c609,610
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 6386 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 6160 96.46% 96.46% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 226 3.54% 100.00% # Request fanout histogram
607c613
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram