| 1Redirecting stdout to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl/simout
2Redirecting stderr to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl/simerr
|
1gem5 Simulator System. http://gem5.org
2gem5 is copyrighted software; use the --copyright option for details.
3
| 3gem5 Simulator System. http://gem5.org
4gem5 is copyrighted software; use the --copyright option for details.
5
|
4gem5 compiled Jan 21 2016 14:20:17
5gem5 started Jan 21 2016 14:20:32
6gem5 executing on zizzer, pid 63117
7command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl -re /z/atgutier/gem5/gem5-commit/tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl
| 6gem5 compiled Oct 13 2016 20:37:50
7gem5 started Oct 13 2016 20:38:05
8gem5 executing on e108600-lin, pid 342
9command line: /work/curdun01/gem5-external.hg/build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-dram-ctrl -re /work/curdun01/gem5-external.hg/tests/testing/../run.py quick/se/70.tgen/null/none/tgen-dram-ctrl
|
8
9Global frequency set at 1000000000000 ticks per second
10info: Entering event queue @ 0. Starting simulation...
11Exiting @ tick 100000000000 because simulate() limit reached
| 10
11Global frequency set at 1000000000000 ticks per second
12info: Entering event queue @ 0. Starting simulation...
13Exiting @ tick 100000000000 because simulate() limit reached
|