| config.ini (11440:76b5639162af) | config.ini (11680:b4d943429dc6) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu dvfs_handler membus monitor physmem 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu dvfs_handler membus monitor physmem 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain |
| 17default_p_state=UNDEFINED |
|
| 17eventq_index=0 18exit_on_work_items=false 19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false 28multi_thread=false 29num_work_ids=16 | 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 |
| 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null |
|
| 30readfile= 31symbolfile= 32thermal_components= 33thermal_model=Null 34work_begin_ckpt_count=0 35work_begin_cpu_id_exit=-1 36work_begin_exit_count=0 37work_cpus_ckpt_count=0 --- 14 unchanged lines hidden (view full) --- 52[system.clk_domain.voltage_domain] 53type=VoltageDomain 54eventq_index=0 55voltage=1.000000 56 57[system.cpu] 58type=TrafficGen 59clk_domain=system.clk_domain | 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 --- 14 unchanged lines hidden (view full) --- 57[system.clk_domain.voltage_domain] 58type=VoltageDomain 59eventq_index=0 60voltage=1.000000 61 62[system.cpu] 63type=TrafficGen 64clk_domain=system.clk_domain |
| 60config_file=tests/quick/se/70.tgen/tgen-dram-ctrl.cfg | 65config_file=/work/curdun01/gem5-external.hg/tests/testing/../../tests/quick/se/70.tgen/tgen-dram-ctrl.cfg 66default_p_state=UNDEFINED |
| 61elastic_req=false 62eventq_index=0 | 67elastic_req=false 68eventq_index=0 |
| 69p_state_clk_gate_bins=20 70p_state_clk_gate_max=1000000000000 71p_state_clk_gate_min=1000 72power_model=Null 73progress_check=1000000000 |
|
| 63system=system 64port=system.monitor.slave 65 66[system.dvfs_handler] 67type=DVFSHandler 68domains= 69enable=false 70eventq_index=0 71sys_clk_domain=system.clk_domain 72transition_latency=100000000 73 74[system.membus] 75type=NoncoherentXBar 76clk_domain=system.clk_domain | 74system=system 75port=system.monitor.slave 76 77[system.dvfs_handler] 78type=DVFSHandler 79domains= 80enable=false 81eventq_index=0 82sys_clk_domain=system.clk_domain 83transition_latency=100000000 84 85[system.membus] 86type=NoncoherentXBar 87clk_domain=system.clk_domain |
| 88default_p_state=UNDEFINED |
|
| 77eventq_index=0 78forward_latency=1 79frontend_latency=2 | 89eventq_index=0 90forward_latency=1 91frontend_latency=2 |
| 92p_state_clk_gate_bins=20 93p_state_clk_gate_max=1000000000000 94p_state_clk_gate_min=1000 95power_model=Null |
|
| 80response_latency=2 81use_default_range=false 82width=16 83master=system.physmem.port 84slave=system.monitor.master system.system_port 85 86[system.monitor] 87type=CommMonitor 88bandwidth_bins=20 89burst_length_bins=20 90clk_domain=system.clk_domain | 96response_latency=2 97use_default_range=false 98width=16 99master=system.physmem.port 100slave=system.monitor.master system.system_port 101 102[system.monitor] 103type=CommMonitor 104bandwidth_bins=20 105burst_length_bins=20 106clk_domain=system.clk_domain |
| 107default_p_state=UNDEFINED |
|
| 91disable_addr_dists=true 92disable_bandwidth_hists=false 93disable_burst_length_hists=false 94disable_itt_dists=false 95disable_latency_hists=false 96disable_outstanding_hists=false 97disable_transaction_hists=false 98eventq_index=0 99itt_bins=20 100itt_max_bin=100000 101latency_bins=20 102outstanding_bins=20 | 108disable_addr_dists=true 109disable_bandwidth_hists=false 110disable_burst_length_hists=false 111disable_itt_dists=false 112disable_latency_hists=false 113disable_outstanding_hists=false 114disable_transaction_hists=false 115eventq_index=0 116itt_bins=20 117itt_max_bin=100000 118latency_bins=20 119outstanding_bins=20 |
| 120p_state_clk_gate_bins=20 121p_state_clk_gate_max=1000000000000 122p_state_clk_gate_min=1000 123power_model=Null |
|
| 103read_addr_mask=18446744073709551615 104sample_period=1000000000 105system=system 106transaction_bins=20 107write_addr_mask=18446744073709551615 108master=system.membus.slave[0] 109slave=system.cpu.port 110 111[system.physmem] 112type=DRAMCtrl | 124read_addr_mask=18446744073709551615 125sample_period=1000000000 126system=system 127transaction_bins=20 128write_addr_mask=18446744073709551615 129master=system.membus.slave[0] 130slave=system.cpu.port 131 132[system.physmem] 133type=DRAMCtrl |
| 113IDD0=0.075000 | 134IDD0=0.055000 |
| 114IDD02=0.000000 | 135IDD02=0.000000 |
| 115IDD2N=0.050000 | 136IDD2N=0.032000 |
| 116IDD2N2=0.000000 117IDD2P0=0.000000 118IDD2P02=0.000000 | 137IDD2N2=0.000000 138IDD2P0=0.000000 139IDD2P02=0.000000 |
| 119IDD2P1=0.000000 | 140IDD2P1=0.032000 |
| 120IDD2P12=0.000000 | 141IDD2P12=0.000000 |
| 121IDD3N=0.057000 | 142IDD3N=0.038000 |
| 122IDD3N2=0.000000 123IDD3P0=0.000000 124IDD3P02=0.000000 | 143IDD3N2=0.000000 144IDD3P0=0.000000 145IDD3P02=0.000000 |
| 125IDD3P1=0.000000 | 146IDD3P1=0.038000 |
| 126IDD3P12=0.000000 | 147IDD3P12=0.000000 |
| 127IDD4R=0.187000 | 148IDD4R=0.157000 |
| 128IDD4R2=0.000000 | 149IDD4R2=0.000000 |
| 129IDD4W=0.165000 | 150IDD4W=0.125000 |
| 130IDD4W2=0.000000 | 151IDD4W2=0.000000 |
| 131IDD5=0.220000 | 152IDD5=0.235000 |
| 132IDD52=0.000000 | 153IDD52=0.000000 |
| 133IDD6=0.000000 | 154IDD6=0.020000 |
| 134IDD62=0.000000 135VDD=1.500000 136VDD2=0.000000 137activation_limit=4 138addr_mapping=RoRaBaCoCh 139bank_groups_per_rank=0 140banks_per_rank=8 141burst_length=8 142channels=1 143clk_domain=system.clk_domain 144conf_table_reported=true | 155IDD62=0.000000 156VDD=1.500000 157VDD2=0.000000 158activation_limit=4 159addr_mapping=RoRaBaCoCh 160bank_groups_per_rank=0 161banks_per_rank=8 162burst_length=8 163channels=1 164clk_domain=system.clk_domain 165conf_table_reported=true |
| 166default_p_state=UNDEFINED |
|
| 145device_bus_width=8 146device_rowbuffer_size=1024 147device_size=536870912 148devices_per_rank=8 149dll=true 150eventq_index=0 151in_addr_map=true | 167device_bus_width=8 168device_rowbuffer_size=1024 169device_size=536870912 170devices_per_rank=8 171dll=true 172eventq_index=0 173in_addr_map=true |
| 174kvm_map=true |
|
| 152max_accesses_per_row=16 153mem_sched_policy=frfcfs 154min_writes_per_switch=16 155null=false | 175max_accesses_per_row=16 176mem_sched_policy=frfcfs 177min_writes_per_switch=16 178null=false |
| 179p_state_clk_gate_bins=20 180p_state_clk_gate_max=1000000000000 181p_state_clk_gate_min=1000 |
|
| 156page_policy=open_adaptive | 182page_policy=open_adaptive |
| 157range=0:134217727 | 183power_model=Null 184range=0:134217727:0:0:0:0 |
| 158ranks_per_channel=2 159read_buffer_size=32 160static_backend_latency=10000 161static_frontend_latency=10000 162tBURST=5000 163tCCD_L=0 164tCK=1250 165tCL=13750 --- 5 unchanged lines hidden (view full) --- 171tRP=13750 172tRRD=6000 173tRRD_L=0 174tRTP=7500 175tRTW=2500 176tWR=15000 177tWTR=7500 178tXAW=30000 | 185ranks_per_channel=2 186read_buffer_size=32 187static_backend_latency=10000 188static_frontend_latency=10000 189tBURST=5000 190tCCD_L=0 191tCK=1250 192tCL=13750 --- 5 unchanged lines hidden (view full) --- 198tRP=13750 199tRRD=6000 200tRRD_L=0 201tRTP=7500 202tRTW=2500 203tWR=15000 204tWTR=7500 205tXAW=30000 |
| 179tXP=0 | 206tXP=6000 |
| 180tXPDLL=0 | 207tXPDLL=0 |
| 181tXS=0 | 208tXS=270000 |
| 182tXSDLL=0 183write_buffer_size=64 184write_high_thresh_perc=85 185write_low_thresh_perc=50 186port=system.membus.master[0] 187 | 209tXSDLL=0 210write_buffer_size=64 211write_high_thresh_perc=85 212write_low_thresh_perc=50 213port=system.membus.master[0] 214 |