| config.ini (10218:5a45f124a2f7) | config.ini (10315:9e02c14446bb) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System |
| 13children=clk_domain cpu membus monitor physmem | 13children=clk_domain cpu dvfs_handler membus monitor physmem |
| 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= | 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= |
| 20kernel_addr_check=true |
|
| 20load_addr_mask=1099511627775 | 21load_addr_mask=1099511627775 |
| 22load_offset=0 |
|
| 21mem_mode=timing 22mem_ranges= 23memories=system.physmem 24num_work_ids=16 25readfile= 26symbolfile= 27work_begin_ckpt_count=0 28work_begin_cpu_id_exit=-1 29work_begin_exit_count=0 30work_cpus_ckpt_count=0 31work_end_ckpt_count=0 32work_end_exit_count=0 33work_item_id=-1 34system_port=system.membus.slave[1] 35 36[system.clk_domain] 37type=SrcClockDomain 38children=voltage_domain 39clock=1000 | 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26num_work_ids=16 27readfile= 28symbolfile= 29work_begin_ckpt_count=0 30work_begin_cpu_id_exit=-1 31work_begin_exit_count=0 32work_cpus_ckpt_count=0 33work_end_ckpt_count=0 34work_end_exit_count=0 35work_item_id=-1 36system_port=system.membus.slave[1] 37 38[system.clk_domain] 39type=SrcClockDomain 40children=voltage_domain 41clock=1000 |
| 42domain_id=-1 |
|
| 40eventq_index=0 | 43eventq_index=0 |
| 44init_perf_level=0 |
|
| 41voltage_domain=system.clk_domain.voltage_domain 42 43[system.clk_domain.voltage_domain] 44type=VoltageDomain 45eventq_index=0 46voltage=1.000000 47 48[system.cpu] 49type=TrafficGen 50clk_domain=system.clk_domain | 45voltage_domain=system.clk_domain.voltage_domain 46 47[system.clk_domain.voltage_domain] 48type=VoltageDomain 49eventq_index=0 50voltage=1.000000 51 52[system.cpu] 53type=TrafficGen 54clk_domain=system.clk_domain |
| 51config_file=tests/quick/se/70.tgen/tgen-simple-dram.cfg | 55config_file=tests/quick/se/70.tgen/tgen-dram-ctrl.cfg |
| 52elastic_req=false 53eventq_index=0 54system=system 55port=system.monitor.slave 56 | 56elastic_req=false 57eventq_index=0 58system=system 59port=system.monitor.slave 60 |
| 61[system.dvfs_handler] 62type=DVFSHandler 63domains= 64enable=false 65eventq_index=0 66sys_clk_domain=system.clk_domain 67transition_latency=100000000 68 |
|
| 57[system.membus] 58type=NoncoherentBus 59clk_domain=system.clk_domain 60eventq_index=0 61header_cycles=1 62use_default_range=false 63width=16 64master=system.physmem.port --- 13 unchanged lines hidden (view full) --- 78disable_transaction_hists=false 79eventq_index=0 80itt_bins=20 81itt_max_bin=100000 82latency_bins=20 83outstanding_bins=20 84read_addr_mask=18446744073709551615 85sample_period=1000000000 | 69[system.membus] 70type=NoncoherentBus 71clk_domain=system.clk_domain 72eventq_index=0 73header_cycles=1 74use_default_range=false 75width=16 76master=system.physmem.port --- 13 unchanged lines hidden (view full) --- 90disable_transaction_hists=false 91eventq_index=0 92itt_bins=20 93itt_max_bin=100000 94latency_bins=20 95outstanding_bins=20 96read_addr_mask=18446744073709551615 97sample_period=1000000000 |
| 98system=system 99trace_compress=true 100trace_enable=false |
|
| 86trace_file= 87transaction_bins=20 88write_addr_mask=18446744073709551615 89master=system.membus.slave[0] 90slave=system.cpu.port 91 92[system.physmem] | 101trace_file= 102transaction_bins=20 103write_addr_mask=18446744073709551615 104master=system.membus.slave[0] 105slave=system.cpu.port 106 107[system.physmem] |
| 93type=SimpleDRAM | 108type=DRAMCtrl |
| 94activation_limit=4 | 109activation_limit=4 |
| 95addr_mapping=RaBaChCo | 110addr_mapping=RoRaBaChCo |
| 96banks_per_rank=8 97burst_length=8 98channels=1 99clk_domain=system.clk_domain 100conf_table_reported=true 101device_bus_width=8 102device_rowbuffer_size=1024 103devices_per_rank=8 104eventq_index=0 105in_addr_map=true | 111banks_per_rank=8 112burst_length=8 113channels=1 114clk_domain=system.clk_domain 115conf_table_reported=true 116device_bus_width=8 117device_rowbuffer_size=1024 118devices_per_rank=8 119eventq_index=0 120in_addr_map=true |
| 121max_accesses_per_row=16 |
|
| 106mem_sched_policy=frfcfs | 122mem_sched_policy=frfcfs |
| 123min_writes_per_switch=16 |
|
| 107null=false | 124null=false |
| 108page_policy=open | 125page_policy=open_adaptive |
| 109range=0:134217727 110ranks_per_channel=2 111read_buffer_size=32 112static_backend_latency=10000 113static_frontend_latency=10000 114tBURST=5000 | 126range=0:134217727 127ranks_per_channel=2 128read_buffer_size=32 129static_backend_latency=10000 130static_frontend_latency=10000 131tBURST=5000 |
| 132tCK=1250 |
|
| 115tCL=13750 116tRAS=35000 117tRCD=13750 118tREFI=7800000 | 133tCL=13750 134tRAS=35000 135tRCD=13750 136tREFI=7800000 |
| 119tRFC=300000 | 137tRFC=260000 |
| 120tRP=13750 | 138tRP=13750 |
| 121tRRD=6250 | 139tRRD=6000 140tRTP=7500 141tRTW=2500 142tWR=15000 |
| 122tWTR=7500 | 143tWTR=7500 |
| 123tXAW=40000 124write_buffer_size=32 125write_high_thresh_perc=70 126write_low_thresh_perc=0 | 144tXAW=30000 145write_buffer_size=64 146write_high_thresh_perc=85 147write_low_thresh_perc=50 |
| 127port=system.membus.master[0] 128 | 148port=system.membus.master[0] 149 |