16a17
> default_p_state=UNDEFINED
29a31,34
> p_state_clk_gate_bins=20
> p_state_clk_gate_max=1000000000000
> p_state_clk_gate_min=1000
> power_model=Null
60c65,66
< config_file=tests/quick/se/70.tgen/tgen-dram-ctrl.cfg
---
> config_file=/work/curdun01/gem5-external.hg/tests/testing/../../tests/quick/se/70.tgen/tgen-dram-ctrl.cfg
> default_p_state=UNDEFINED
62a69,73
> p_state_clk_gate_bins=20
> p_state_clk_gate_max=1000000000000
> p_state_clk_gate_min=1000
> power_model=Null
> progress_check=1000000000
76a88
> default_p_state=UNDEFINED
79a92,95
> p_state_clk_gate_bins=20
> p_state_clk_gate_max=1000000000000
> p_state_clk_gate_min=1000
> power_model=Null
90a107
> default_p_state=UNDEFINED
102a120,123
> p_state_clk_gate_bins=20
> p_state_clk_gate_max=1000000000000
> p_state_clk_gate_min=1000
> power_model=Null
113c134
< IDD0=0.075000
---
> IDD0=0.055000
115c136
< IDD2N=0.050000
---
> IDD2N=0.032000
119c140
< IDD2P1=0.000000
---
> IDD2P1=0.032000
121c142
< IDD3N=0.057000
---
> IDD3N=0.038000
125c146
< IDD3P1=0.000000
---
> IDD3P1=0.038000
127c148
< IDD4R=0.187000
---
> IDD4R=0.157000
129c150
< IDD4W=0.165000
---
> IDD4W=0.125000
131c152
< IDD5=0.220000
---
> IDD5=0.235000
133c154
< IDD6=0.000000
---
> IDD6=0.020000
144a166
> default_p_state=UNDEFINED
151a174
> kvm_map=true
155a179,181
> p_state_clk_gate_bins=20
> p_state_clk_gate_max=1000000000000
> p_state_clk_gate_min=1000
157c183,184
< range=0:134217727
---
> power_model=Null
> range=0:134217727:0:0:0:0
179c206
< tXP=0
---
> tXP=6000
181c208
< tXS=0
---
> tXS=270000