| config.ini (11440:76b5639162af) | config.ini (11570:4aac82f10951) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain |
| 17default_p_state=UNDEFINED |
|
| 17eventq_index=0 18exit_on_work_items=false 19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false 28multi_thread=false 29num_work_ids=16 | 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 |
| 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null |
|
| 30readfile= 31symbolfile= 32thermal_components= 33thermal_model=Null 34work_begin_ckpt_count=0 35work_begin_cpu_id_exit=-1 36work_begin_exit_count=0 37work_cpus_ckpt_count=0 --- 12 unchanged lines hidden (view full) --- 50 51[system.cpu] 52type=TimingSimpleCPU 53children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload 54branchPred=Null 55checker=Null 56clk_domain=system.cpu_clk_domain 57cpu_id=0 | 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 --- 12 unchanged lines hidden (view full) --- 55 56[system.cpu] 57type=TimingSimpleCPU 58children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload 59branchPred=Null 60checker=Null 61clk_domain=system.cpu_clk_domain 62cpu_id=0 |
| 63default_p_state=UNDEFINED |
|
| 58do_checkpoint_insts=true 59do_quiesce=true 60do_statistics_insts=true 61dtb=system.cpu.dtb 62eventq_index=0 63function_trace=false 64function_trace_start=0 65interrupts=system.cpu.interrupts 66isa=system.cpu.isa 67itb=system.cpu.itb 68max_insts_all_threads=0 69max_insts_any_thread=0 70max_loads_all_threads=0 71max_loads_any_thread=0 72numThreads=1 | 64do_checkpoint_insts=true 65do_quiesce=true 66do_statistics_insts=true 67dtb=system.cpu.dtb 68eventq_index=0 69function_trace=false 70function_trace_start=0 71interrupts=system.cpu.interrupts 72isa=system.cpu.isa 73itb=system.cpu.itb 74max_insts_all_threads=0 75max_insts_any_thread=0 76max_loads_all_threads=0 77max_loads_any_thread=0 78numThreads=1 |
| 79p_state_clk_gate_bins=20 80p_state_clk_gate_max=1000000000000 81p_state_clk_gate_min=1000 82power_model=Null |
|
| 73profile=0 74progress_interval=0 75simpoint_start_insts= 76socket_id=0 77switched_out=false 78system=system 79tracer=system.cpu.tracer 80workload=system.cpu.workload 81dcache_port=system.cpu.dcache.cpu_side 82icache_port=system.cpu.icache.cpu_side 83 84[system.cpu.dcache] 85type=Cache 86children=tags 87addr_ranges=0:18446744073709551615 88assoc=2 89clk_domain=system.cpu_clk_domain 90clusivity=mostly_incl | 83profile=0 84progress_interval=0 85simpoint_start_insts= 86socket_id=0 87switched_out=false 88system=system 89tracer=system.cpu.tracer 90workload=system.cpu.workload 91dcache_port=system.cpu.dcache.cpu_side 92icache_port=system.cpu.icache.cpu_side 93 94[system.cpu.dcache] 95type=Cache 96children=tags 97addr_ranges=0:18446744073709551615 98assoc=2 99clk_domain=system.cpu_clk_domain 100clusivity=mostly_incl |
| 101default_p_state=UNDEFINED |
|
| 91demand_mshr_reserve=1 92eventq_index=0 93hit_latency=2 94is_read_only=false 95max_miss_count=0 96mshrs=4 | 102demand_mshr_reserve=1 103eventq_index=0 104hit_latency=2 105is_read_only=false 106max_miss_count=0 107mshrs=4 |
| 108p_state_clk_gate_bins=20 109p_state_clk_gate_max=1000000000000 110p_state_clk_gate_min=1000 111power_model=Null |
|
| 97prefetch_on_access=false 98prefetcher=Null 99response_latency=2 100sequential_access=false 101size=262144 102system=system 103tags=system.cpu.dcache.tags 104tgts_per_mshr=20 105write_buffers=8 106writeback_clean=false 107cpu_side=system.cpu.dcache_port 108mem_side=system.cpu.toL2Bus.slave[1] 109 110[system.cpu.dcache.tags] 111type=LRU 112assoc=2 113block_size=64 114clk_domain=system.cpu_clk_domain | 112prefetch_on_access=false 113prefetcher=Null 114response_latency=2 115sequential_access=false 116size=262144 117system=system 118tags=system.cpu.dcache.tags 119tgts_per_mshr=20 120write_buffers=8 121writeback_clean=false 122cpu_side=system.cpu.dcache_port 123mem_side=system.cpu.toL2Bus.slave[1] 124 125[system.cpu.dcache.tags] 126type=LRU 127assoc=2 128block_size=64 129clk_domain=system.cpu_clk_domain |
| 130default_p_state=UNDEFINED |
|
| 115eventq_index=0 116hit_latency=2 | 131eventq_index=0 132hit_latency=2 |
| 133p_state_clk_gate_bins=20 134p_state_clk_gate_max=1000000000000 135p_state_clk_gate_min=1000 136power_model=Null |
|
| 117sequential_access=false 118size=262144 119 120[system.cpu.dtb] 121type=SparcTLB 122eventq_index=0 123size=64 124 125[system.cpu.icache] 126type=Cache 127children=tags 128addr_ranges=0:18446744073709551615 129assoc=2 130clk_domain=system.cpu_clk_domain 131clusivity=mostly_incl | 137sequential_access=false 138size=262144 139 140[system.cpu.dtb] 141type=SparcTLB 142eventq_index=0 143size=64 144 145[system.cpu.icache] 146type=Cache 147children=tags 148addr_ranges=0:18446744073709551615 149assoc=2 150clk_domain=system.cpu_clk_domain 151clusivity=mostly_incl |
| 152default_p_state=UNDEFINED |
|
| 132demand_mshr_reserve=1 133eventq_index=0 134hit_latency=2 135is_read_only=true 136max_miss_count=0 137mshrs=4 | 153demand_mshr_reserve=1 154eventq_index=0 155hit_latency=2 156is_read_only=true 157max_miss_count=0 158mshrs=4 |
| 159p_state_clk_gate_bins=20 160p_state_clk_gate_max=1000000000000 161p_state_clk_gate_min=1000 162power_model=Null |
|
| 138prefetch_on_access=false 139prefetcher=Null 140response_latency=2 141sequential_access=false 142size=131072 143system=system 144tags=system.cpu.icache.tags 145tgts_per_mshr=20 146write_buffers=8 147writeback_clean=true 148cpu_side=system.cpu.icache_port 149mem_side=system.cpu.toL2Bus.slave[0] 150 151[system.cpu.icache.tags] 152type=LRU 153assoc=2 154block_size=64 155clk_domain=system.cpu_clk_domain | 163prefetch_on_access=false 164prefetcher=Null 165response_latency=2 166sequential_access=false 167size=131072 168system=system 169tags=system.cpu.icache.tags 170tgts_per_mshr=20 171write_buffers=8 172writeback_clean=true 173cpu_side=system.cpu.icache_port 174mem_side=system.cpu.toL2Bus.slave[0] 175 176[system.cpu.icache.tags] 177type=LRU 178assoc=2 179block_size=64 180clk_domain=system.cpu_clk_domain |
| 181default_p_state=UNDEFINED |
|
| 156eventq_index=0 157hit_latency=2 | 182eventq_index=0 183hit_latency=2 |
| 184p_state_clk_gate_bins=20 185p_state_clk_gate_max=1000000000000 186p_state_clk_gate_min=1000 187power_model=Null |
|
| 158sequential_access=false 159size=131072 160 161[system.cpu.interrupts] 162type=SparcInterrupts 163eventq_index=0 164 165[system.cpu.isa] --- 7 unchanged lines hidden (view full) --- 173 174[system.cpu.l2cache] 175type=Cache 176children=tags 177addr_ranges=0:18446744073709551615 178assoc=8 179clk_domain=system.cpu_clk_domain 180clusivity=mostly_incl | 188sequential_access=false 189size=131072 190 191[system.cpu.interrupts] 192type=SparcInterrupts 193eventq_index=0 194 195[system.cpu.isa] --- 7 unchanged lines hidden (view full) --- 203 204[system.cpu.l2cache] 205type=Cache 206children=tags 207addr_ranges=0:18446744073709551615 208assoc=8 209clk_domain=system.cpu_clk_domain 210clusivity=mostly_incl |
| 211default_p_state=UNDEFINED |
|
| 181demand_mshr_reserve=1 182eventq_index=0 183hit_latency=20 184is_read_only=false 185max_miss_count=0 186mshrs=20 | 212demand_mshr_reserve=1 213eventq_index=0 214hit_latency=20 215is_read_only=false 216max_miss_count=0 217mshrs=20 |
| 218p_state_clk_gate_bins=20 219p_state_clk_gate_max=1000000000000 220p_state_clk_gate_min=1000 221power_model=Null |
|
| 187prefetch_on_access=false 188prefetcher=Null 189response_latency=20 190sequential_access=false 191size=2097152 192system=system 193tags=system.cpu.l2cache.tags 194tgts_per_mshr=12 195write_buffers=8 196writeback_clean=false 197cpu_side=system.cpu.toL2Bus.master[0] 198mem_side=system.membus.slave[1] 199 200[system.cpu.l2cache.tags] 201type=LRU 202assoc=8 203block_size=64 204clk_domain=system.cpu_clk_domain | 222prefetch_on_access=false 223prefetcher=Null 224response_latency=20 225sequential_access=false 226size=2097152 227system=system 228tags=system.cpu.l2cache.tags 229tgts_per_mshr=12 230write_buffers=8 231writeback_clean=false 232cpu_side=system.cpu.toL2Bus.master[0] 233mem_side=system.membus.slave[1] 234 235[system.cpu.l2cache.tags] 236type=LRU 237assoc=8 238block_size=64 239clk_domain=system.cpu_clk_domain |
| 240default_p_state=UNDEFINED |
|
| 205eventq_index=0 206hit_latency=20 | 241eventq_index=0 242hit_latency=20 |
| 243p_state_clk_gate_bins=20 244p_state_clk_gate_max=1000000000000 245p_state_clk_gate_min=1000 246power_model=Null |
|
| 207sequential_access=false 208size=2097152 209 210[system.cpu.toL2Bus] 211type=CoherentXBar 212children=snoop_filter 213clk_domain=system.cpu_clk_domain | 247sequential_access=false 248size=2097152 249 250[system.cpu.toL2Bus] 251type=CoherentXBar 252children=snoop_filter 253clk_domain=system.cpu_clk_domain |
| 254default_p_state=UNDEFINED |
|
| 214eventq_index=0 215forward_latency=0 216frontend_latency=1 | 255eventq_index=0 256forward_latency=0 257frontend_latency=1 |
| 258p_state_clk_gate_bins=20 259p_state_clk_gate_max=1000000000000 260p_state_clk_gate_min=1000 |
|
| 217point_of_coherency=false | 261point_of_coherency=false |
| 262power_model=Null |
|
| 218response_latency=1 219snoop_filter=system.cpu.toL2Bus.snoop_filter 220snoop_response_latency=1 221system=system 222use_default_range=false 223width=32 224master=system.cpu.l2cache.cpu_side 225slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side --- 14 unchanged lines hidden (view full) --- 240cmd=vortex bendian.raw 241cwd=build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing 242drivers= 243egid=100 244env= 245errout=cerr 246euid=100 247eventq_index=0 | 263response_latency=1 264snoop_filter=system.cpu.toL2Bus.snoop_filter 265snoop_response_latency=1 266system=system 267use_default_range=false 268width=32 269master=system.cpu.l2cache.cpu_side 270slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side --- 14 unchanged lines hidden (view full) --- 285cmd=vortex bendian.raw 286cwd=build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing 287drivers= 288egid=100 289env= 290errout=cerr 291euid=100 292eventq_index=0 |
| 248executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/vortex | 293executable=/arm/projectscratch/randd/systems/dist/cpu2000/binaries/sparc/linux/vortex |
| 249gid=100 250input=cin 251kvmInSE=false 252max_stack_size=67108864 253output=cout 254pid=100 255ppid=99 256simpoint=0 --- 15 unchanged lines hidden (view full) --- 272enable=false 273eventq_index=0 274sys_clk_domain=system.clk_domain 275transition_latency=100000000 276 277[system.membus] 278type=CoherentXBar 279clk_domain=system.clk_domain | 294gid=100 295input=cin 296kvmInSE=false 297max_stack_size=67108864 298output=cout 299pid=100 300ppid=99 301simpoint=0 --- 15 unchanged lines hidden (view full) --- 317enable=false 318eventq_index=0 319sys_clk_domain=system.clk_domain 320transition_latency=100000000 321 322[system.membus] 323type=CoherentXBar 324clk_domain=system.clk_domain |
| 325default_p_state=UNDEFINED |
|
| 280eventq_index=0 281forward_latency=4 282frontend_latency=3 | 326eventq_index=0 327forward_latency=4 328frontend_latency=3 |
| 329p_state_clk_gate_bins=20 330p_state_clk_gate_max=1000000000000 331p_state_clk_gate_min=1000 |
|
| 283point_of_coherency=true | 332point_of_coherency=true |
| 333power_model=Null |
|
| 284response_latency=2 285snoop_filter=Null 286snoop_response_latency=4 287system=system 288use_default_range=false 289width=16 290master=system.physmem.port 291slave=system.system_port system.cpu.l2cache.mem_side 292 293[system.physmem] 294type=SimpleMemory 295bandwidth=73.000000 296clk_domain=system.clk_domain 297conf_table_reported=true | 334response_latency=2 335snoop_filter=Null 336snoop_response_latency=4 337system=system 338use_default_range=false 339width=16 340master=system.physmem.port 341slave=system.system_port system.cpu.l2cache.mem_side 342 343[system.physmem] 344type=SimpleMemory 345bandwidth=73.000000 346clk_domain=system.clk_domain 347conf_table_reported=true |
| 348default_p_state=UNDEFINED |
|
| 298eventq_index=0 299in_addr_map=true 300latency=30000 301latency_var=0 302null=false | 349eventq_index=0 350in_addr_map=true 351latency=30000 352latency_var=0 353null=false |
| 354p_state_clk_gate_bins=20 355p_state_clk_gate_max=1000000000000 356p_state_clk_gate_min=1000 357power_model=Null |
|
| 303range=0:134217727 304port=system.membus.master[0] 305 306[system.voltage_domain] 307type=VoltageDomain 308eventq_index=0 309voltage=1.000000 310 | 358range=0:134217727 359port=system.membus.master[0] 360 361[system.voltage_domain] 362type=VoltageDomain 363eventq_index=0 364voltage=1.000000 365 |