| config.ini (10752:62b24818c8c6) | config.ini (10900:ac6617bf9967) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 9 unchanged lines hidden (view full) --- 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 9 unchanged lines hidden (view full) --- 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem |
| 26mmap_using_noreserve=false |
|
| 26num_work_ids=16 27readfile= 28symbolfile= 29work_begin_ckpt_count=0 30work_begin_cpu_id_exit=-1 31work_begin_exit_count=0 32work_cpus_ckpt_count=0 33work_end_ckpt_count=0 --- 43 unchanged lines hidden (view full) --- 77icache_port=system.cpu.icache.cpu_side 78 79[system.cpu.dcache] 80type=BaseCache 81children=tags 82addr_ranges=0:18446744073709551615 83assoc=2 84clk_domain=system.cpu_clk_domain | 27num_work_ids=16 28readfile= 29symbolfile= 30work_begin_ckpt_count=0 31work_begin_cpu_id_exit=-1 32work_begin_exit_count=0 33work_cpus_ckpt_count=0 34work_end_ckpt_count=0 --- 43 unchanged lines hidden (view full) --- 78icache_port=system.cpu.icache.cpu_side 79 80[system.cpu.dcache] 81type=BaseCache 82children=tags 83addr_ranges=0:18446744073709551615 84assoc=2 85clk_domain=system.cpu_clk_domain |
| 86demand_mshr_reserve=1 |
|
| 85eventq_index=0 86forward_snoops=true 87hit_latency=2 | 87eventq_index=0 88forward_snoops=true 89hit_latency=2 |
| 88is_top_level=true | 90is_read_only=false |
| 89max_miss_count=0 90mshrs=4 91prefetch_on_access=false 92prefetcher=Null 93response_latency=2 94sequential_access=false 95size=262144 96system=system 97tags=system.cpu.dcache.tags 98tgts_per_mshr=20 | 91max_miss_count=0 92mshrs=4 93prefetch_on_access=false 94prefetcher=Null 95response_latency=2 96sequential_access=false 97size=262144 98system=system 99tags=system.cpu.dcache.tags 100tgts_per_mshr=20 |
| 99two_queue=false | |
| 100write_buffers=8 101cpu_side=system.cpu.dcache_port 102mem_side=system.cpu.toL2Bus.slave[1] 103 104[system.cpu.dcache.tags] 105type=LRU 106assoc=2 107block_size=64 --- 9 unchanged lines hidden (view full) --- 117size=64 118 119[system.cpu.icache] 120type=BaseCache 121children=tags 122addr_ranges=0:18446744073709551615 123assoc=2 124clk_domain=system.cpu_clk_domain | 101write_buffers=8 102cpu_side=system.cpu.dcache_port 103mem_side=system.cpu.toL2Bus.slave[1] 104 105[system.cpu.dcache.tags] 106type=LRU 107assoc=2 108block_size=64 --- 9 unchanged lines hidden (view full) --- 118size=64 119 120[system.cpu.icache] 121type=BaseCache 122children=tags 123addr_ranges=0:18446744073709551615 124assoc=2 125clk_domain=system.cpu_clk_domain |
| 126demand_mshr_reserve=1 |
|
| 125eventq_index=0 126forward_snoops=true 127hit_latency=2 | 127eventq_index=0 128forward_snoops=true 129hit_latency=2 |
| 128is_top_level=true | 130is_read_only=true |
| 129max_miss_count=0 130mshrs=4 131prefetch_on_access=false 132prefetcher=Null 133response_latency=2 134sequential_access=false 135size=131072 136system=system 137tags=system.cpu.icache.tags 138tgts_per_mshr=20 | 131max_miss_count=0 132mshrs=4 133prefetch_on_access=false 134prefetcher=Null 135response_latency=2 136sequential_access=false 137size=131072 138system=system 139tags=system.cpu.icache.tags 140tgts_per_mshr=20 |
| 139two_queue=false | |
| 140write_buffers=8 141cpu_side=system.cpu.icache_port 142mem_side=system.cpu.toL2Bus.slave[0] 143 144[system.cpu.icache.tags] 145type=LRU 146assoc=2 147block_size=64 --- 17 unchanged lines hidden (view full) --- 165size=64 166 167[system.cpu.l2cache] 168type=BaseCache 169children=tags 170addr_ranges=0:18446744073709551615 171assoc=8 172clk_domain=system.cpu_clk_domain | 141write_buffers=8 142cpu_side=system.cpu.icache_port 143mem_side=system.cpu.toL2Bus.slave[0] 144 145[system.cpu.icache.tags] 146type=LRU 147assoc=2 148block_size=64 --- 17 unchanged lines hidden (view full) --- 166size=64 167 168[system.cpu.l2cache] 169type=BaseCache 170children=tags 171addr_ranges=0:18446744073709551615 172assoc=8 173clk_domain=system.cpu_clk_domain |
| 174demand_mshr_reserve=1 |
|
| 173eventq_index=0 174forward_snoops=true 175hit_latency=20 | 175eventq_index=0 176forward_snoops=true 177hit_latency=20 |
| 176is_top_level=false | 178is_read_only=false |
| 177max_miss_count=0 178mshrs=20 179prefetch_on_access=false 180prefetcher=Null 181response_latency=20 182sequential_access=false 183size=2097152 184system=system 185tags=system.cpu.l2cache.tags 186tgts_per_mshr=12 | 179max_miss_count=0 180mshrs=20 181prefetch_on_access=false 182prefetcher=Null 183response_latency=20 184sequential_access=false 185size=2097152 186system=system 187tags=system.cpu.l2cache.tags 188tgts_per_mshr=12 |
| 187two_queue=false | |
| 188write_buffers=8 189cpu_side=system.cpu.toL2Bus.master[0] 190mem_side=system.membus.slave[1] 191 192[system.cpu.l2cache.tags] 193type=LRU 194assoc=8 195block_size=64 196clk_domain=system.cpu_clk_domain 197eventq_index=0 198hit_latency=20 199sequential_access=false 200size=2097152 201 202[system.cpu.toL2Bus] 203type=CoherentXBar 204clk_domain=system.cpu_clk_domain 205eventq_index=0 | 189write_buffers=8 190cpu_side=system.cpu.toL2Bus.master[0] 191mem_side=system.membus.slave[1] 192 193[system.cpu.l2cache.tags] 194type=LRU 195assoc=8 196block_size=64 197clk_domain=system.cpu_clk_domain 198eventq_index=0 199hit_latency=20 200sequential_access=false 201size=2097152 202 203[system.cpu.toL2Bus] 204type=CoherentXBar 205clk_domain=system.cpu_clk_domain 206eventq_index=0 |
| 206header_cycles=1 | 207forward_latency=0 208frontend_latency=1 209response_latency=1 |
| 207snoop_filter=Null | 210snoop_filter=Null |
| 211snoop_response_latency=1 |
|
| 208system=system 209use_default_range=false 210width=32 211master=system.cpu.l2cache.cpu_side 212slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 213 214[system.cpu.tracer] 215type=ExeTracer 216eventq_index=0 217 218[system.cpu.workload] 219type=LiveProcess 220cmd=vortex bendian.raw | 212system=system 213use_default_range=false 214width=32 215master=system.cpu.l2cache.cpu_side 216slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 217 218[system.cpu.tracer] 219type=ExeTracer 220eventq_index=0 221 222[system.cpu.workload] 223type=LiveProcess 224cmd=vortex bendian.raw |
| 221cwd=build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing | 225cwd=build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing 226drivers= |
| 222egid=100 223env= 224errout=cerr 225euid=100 226eventq_index=0 227executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/vortex 228gid=100 229input=cin | 227egid=100 228env= 229errout=cerr 230euid=100 231eventq_index=0 232executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/vortex 233gid=100 234input=cin |
| 235kvmInSE=false |
|
| 230max_stack_size=67108864 231output=cout 232pid=100 233ppid=99 234simpoint=0 235system=system 236uid=100 237useArchPT=false --- 13 unchanged lines hidden (view full) --- 251eventq_index=0 252sys_clk_domain=system.clk_domain 253transition_latency=100000000 254 255[system.membus] 256type=CoherentXBar 257clk_domain=system.clk_domain 258eventq_index=0 | 236max_stack_size=67108864 237output=cout 238pid=100 239ppid=99 240simpoint=0 241system=system 242uid=100 243useArchPT=false --- 13 unchanged lines hidden (view full) --- 257eventq_index=0 258sys_clk_domain=system.clk_domain 259transition_latency=100000000 260 261[system.membus] 262type=CoherentXBar 263clk_domain=system.clk_domain 264eventq_index=0 |
| 259header_cycles=1 | 265forward_latency=4 266frontend_latency=3 267response_latency=2 |
| 260snoop_filter=Null | 268snoop_filter=Null |
| 269snoop_response_latency=4 |
|
| 261system=system 262use_default_range=false | 270system=system 271use_default_range=false |
| 263width=8 | 272width=16 |
| 264master=system.physmem.port 265slave=system.system_port system.cpu.l2cache.mem_side 266 267[system.physmem] 268type=SimpleMemory 269bandwidth=73.000000 270clk_domain=system.clk_domain 271conf_table_reported=true --- 13 unchanged lines hidden --- | 273master=system.physmem.port 274slave=system.system_port system.cpu.l2cache.mem_side 275 276[system.physmem] 277type=SimpleMemory 278bandwidth=73.000000 279clk_domain=system.clk_domain 280conf_table_reported=true --- 13 unchanged lines hidden --- |