1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
--- 74 unchanged lines hidden (view full) ---
83type=Cache
84children=tags
85addr_ranges=0:18446744073709551615
86assoc=2
87clk_domain=system.cpu_clk_domain
88clusivity=mostly_incl
89demand_mshr_reserve=1
90eventq_index=0
91hit_latency=2
92is_read_only=false
93max_miss_count=0
94mshrs=4
95prefetch_on_access=false
96prefetcher=Null
97response_latency=2
98sequential_access=false
--- 25 unchanged lines hidden (view full) ---
124type=Cache
125children=tags
126addr_ranges=0:18446744073709551615
127assoc=2
128clk_domain=system.cpu_clk_domain
129clusivity=mostly_incl
130demand_mshr_reserve=1
131eventq_index=0
132hit_latency=2
133is_read_only=true
134max_miss_count=0
135mshrs=4
136prefetch_on_access=false
137prefetcher=Null
138response_latency=2
139sequential_access=false
--- 33 unchanged lines hidden (view full) ---
173type=Cache
174children=tags
175addr_ranges=0:18446744073709551615
176assoc=8
177clk_domain=system.cpu_clk_domain
178clusivity=mostly_incl
179demand_mshr_reserve=1
180eventq_index=0
181hit_latency=20
182is_read_only=false
183max_miss_count=0
184mshrs=20
185prefetch_on_access=false
186prefetcher=Null
187response_latency=20
188sequential_access=false
--- 18 unchanged lines hidden (view full) ---
207
208[system.cpu.toL2Bus]
209type=CoherentXBar
210children=snoop_filter
211clk_domain=system.cpu_clk_domain
212eventq_index=0
213forward_latency=0
214frontend_latency=1
215point_of_coherency=false
216response_latency=1
217snoop_filter=system.cpu.toL2Bus.snoop_filter
218snoop_response_latency=1
219system=system
220use_default_range=false
221width=32
222master=system.cpu.l2cache.cpu_side
223slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
--- 14 unchanged lines hidden (view full) ---
238cmd=vortex bendian.raw
239cwd=build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing
240drivers=
241egid=100
242env=
243errout=cerr
244euid=100
245eventq_index=0
246executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/vortex
247gid=100
248input=cin
249kvmInSE=false
250max_stack_size=67108864
251output=cout
252pid=100
253ppid=99
254simpoint=0
--- 18 unchanged lines hidden (view full) ---
273transition_latency=100000000
274
275[system.membus]
276type=CoherentXBar
277clk_domain=system.clk_domain
278eventq_index=0
279forward_latency=4
280frontend_latency=3
281point_of_coherency=true
282response_latency=2
283snoop_filter=Null
284snoop_response_latency=4
285system=system
286use_default_range=false
287width=16
288master=system.physmem.port
289slave=system.system_port system.cpu.l2cache.mem_side
--- 19 unchanged lines hidden ---
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
--- 74 unchanged lines hidden (view full) ---
83type=Cache
84children=tags
85addr_ranges=0:18446744073709551615
86assoc=2
87clk_domain=system.cpu_clk_domain
88clusivity=mostly_incl
89demand_mshr_reserve=1
90eventq_index=0
91hit_latency=2
92is_read_only=false
93max_miss_count=0
94mshrs=4
95prefetch_on_access=false
96prefetcher=Null
97response_latency=2
98sequential_access=false
--- 25 unchanged lines hidden (view full) ---
124type=Cache
125children=tags
126addr_ranges=0:18446744073709551615
127assoc=2
128clk_domain=system.cpu_clk_domain
129clusivity=mostly_incl
130demand_mshr_reserve=1
131eventq_index=0
132hit_latency=2
133is_read_only=true
134max_miss_count=0
135mshrs=4
136prefetch_on_access=false
137prefetcher=Null
138response_latency=2
139sequential_access=false
--- 33 unchanged lines hidden (view full) ---
173type=Cache
174children=tags
175addr_ranges=0:18446744073709551615
176assoc=8
177clk_domain=system.cpu_clk_domain
178clusivity=mostly_incl
179demand_mshr_reserve=1
180eventq_index=0
181hit_latency=20
182is_read_only=false
183max_miss_count=0
184mshrs=20
185prefetch_on_access=false
186prefetcher=Null
187response_latency=20
188sequential_access=false
--- 18 unchanged lines hidden (view full) ---
207
208[system.cpu.toL2Bus]
209type=CoherentXBar
210children=snoop_filter
211clk_domain=system.cpu_clk_domain
212eventq_index=0
213forward_latency=0
214frontend_latency=1
215point_of_coherency=false
216response_latency=1
217snoop_filter=system.cpu.toL2Bus.snoop_filter
218snoop_response_latency=1
219system=system
220use_default_range=false
221width=32
222master=system.cpu.l2cache.cpu_side
223slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
--- 14 unchanged lines hidden (view full) ---
238cmd=vortex bendian.raw
239cwd=build/SPARC/tests/opt/quick/se/50.vortex/sparc/linux/simple-timing
240drivers=
241egid=100
242env=
243errout=cerr
244euid=100
245eventq_index=0
246executable=/home/stever/m5/dist/cpu2000/binaries/sparc/linux/vortex
247gid=100
248input=cin
249kvmInSE=false
250max_stack_size=67108864
251output=cout
252pid=100
253ppid=99
254simpoint=0
--- 18 unchanged lines hidden (view full) ---
273transition_latency=100000000
274
275[system.membus]
276type=CoherentXBar
277clk_domain=system.clk_domain
278eventq_index=0
279forward_latency=4
280frontend_latency=3
281point_of_coherency=true
282response_latency=2
283snoop_filter=Null
284snoop_response_latency=4
285system=system
286use_default_range=false
287width=16
288master=system.physmem.port
289slave=system.system_port system.cpu.l2cache.mem_side
--- 19 unchanged lines hidden ---