| config.ini (11570:4aac82f10951) | config.ini (11680:b4d943429dc6) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 9 unchanged lines hidden (view full) --- 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 9 unchanged lines hidden (view full) --- 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing |
| 26mem_ranges=0:536870911 | 26mem_ranges=0:536870911:0:0:0:0 |
| 27memories=system.mem_ctrl 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null --- 62 unchanged lines hidden (view full) --- 97tracer=system.cpu.tracer 98workload=system.cpu.workload 99dcache_port=system.cpu.dcache.cpu_side 100icache_port=system.cpu.icache.cpu_side 101 102[system.cpu.dcache] 103type=Cache 104children=tags | 27memories=system.mem_ctrl 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null --- 62 unchanged lines hidden (view full) --- 97tracer=system.cpu.tracer 98workload=system.cpu.workload 99dcache_port=system.cpu.dcache.cpu_side 100icache_port=system.cpu.icache.cpu_side 101 102[system.cpu.dcache] 103type=Cache 104children=tags |
| 105addr_ranges=0:18446744073709551615 | 105addr_ranges=0:18446744073709551615:0:0:0:0 |
| 106assoc=2 107clk_domain=system.clk_domain 108clusivity=mostly_incl 109default_p_state=UNDEFINED 110demand_mshr_reserve=1 111eventq_index=0 112hit_latency=2 113is_read_only=false --- 79 unchanged lines hidden (view full) --- 193p_state_clk_gate_max=1000000000000 194p_state_clk_gate_min=1000 195power_model=Null 196sys=system 197 198[system.cpu.icache] 199type=Cache 200children=tags | 106assoc=2 107clk_domain=system.clk_domain 108clusivity=mostly_incl 109default_p_state=UNDEFINED 110demand_mshr_reserve=1 111eventq_index=0 112hit_latency=2 113is_read_only=false --- 79 unchanged lines hidden (view full) --- 193p_state_clk_gate_max=1000000000000 194p_state_clk_gate_min=1000 195power_model=Null 196sys=system 197 198[system.cpu.icache] 199type=Cache 200children=tags |
| 201addr_ranges=0:18446744073709551615 | 201addr_ranges=0:18446744073709551615:0:0:0:0 |
| 202assoc=2 203clk_domain=system.clk_domain 204clusivity=mostly_incl 205default_p_state=UNDEFINED 206demand_mshr_reserve=1 207eventq_index=0 208hit_latency=2 209is_read_only=false --- 43 unchanged lines hidden (view full) --- 253id_aa64afr0_el1=0 254id_aa64afr1_el1=0 255id_aa64dfr0_el1=1052678 256id_aa64dfr1_el1=0 257id_aa64isar0_el1=0 258id_aa64isar1_el1=0 259id_aa64mmfr0_el1=15728642 260id_aa64mmfr1_el1=0 | 202assoc=2 203clk_domain=system.clk_domain 204clusivity=mostly_incl 205default_p_state=UNDEFINED 206demand_mshr_reserve=1 207eventq_index=0 208hit_latency=2 209is_read_only=false --- 43 unchanged lines hidden (view full) --- 253id_aa64afr0_el1=0 254id_aa64afr1_el1=0 255id_aa64dfr0_el1=1052678 256id_aa64dfr1_el1=0 257id_aa64isar0_el1=0 258id_aa64isar1_el1=0 259id_aa64mmfr0_el1=15728642 260id_aa64mmfr1_el1=0 |
| 261id_aa64pfr0_el1=17 | 261id_aa64pfr0_el1=34 |
| 262id_aa64pfr1_el1=0 263id_isar0=34607377 264id_isar1=34677009 265id_isar2=555950401 266id_isar3=17899825 267id_isar4=268501314 268id_isar5=0 269id_mmfr0=270536963 --- 118 unchanged lines hidden (view full) --- 388eventq_index=0 389lookup_latency=0 390max_capacity=8388608 391system=system 392 393[system.l2cache] 394type=Cache 395children=tags | 262id_aa64pfr1_el1=0 263id_isar0=34607377 264id_isar1=34677009 265id_isar2=555950401 266id_isar3=17899825 267id_isar4=268501314 268id_isar5=0 269id_mmfr0=270536963 --- 118 unchanged lines hidden (view full) --- 388eventq_index=0 389lookup_latency=0 390max_capacity=8388608 391system=system 392 393[system.l2cache] 394type=Cache 395children=tags |
| 396addr_ranges=0:18446744073709551615 | 396addr_ranges=0:18446744073709551615:0:0:0:0 |
| 397assoc=8 398clk_domain=system.clk_domain 399clusivity=mostly_incl 400default_p_state=UNDEFINED 401demand_mshr_reserve=1 402eventq_index=0 403hit_latency=20 404is_read_only=false --- 28 unchanged lines hidden (view full) --- 433p_state_clk_gate_max=1000000000000 434p_state_clk_gate_min=1000 435power_model=Null 436sequential_access=false 437size=262144 438 439[system.mem_ctrl] 440type=DRAMCtrl | 397assoc=8 398clk_domain=system.clk_domain 399clusivity=mostly_incl 400default_p_state=UNDEFINED 401demand_mshr_reserve=1 402eventq_index=0 403hit_latency=20 404is_read_only=false --- 28 unchanged lines hidden (view full) --- 433p_state_clk_gate_max=1000000000000 434p_state_clk_gate_min=1000 435power_model=Null 436sequential_access=false 437size=262144 438 439[system.mem_ctrl] 440type=DRAMCtrl |
| 441IDD0=0.075000 | 441IDD0=0.055000 |
| 442IDD02=0.000000 | 442IDD02=0.000000 |
| 443IDD2N=0.050000 | 443IDD2N=0.032000 |
| 444IDD2N2=0.000000 445IDD2P0=0.000000 446IDD2P02=0.000000 | 444IDD2N2=0.000000 445IDD2P0=0.000000 446IDD2P02=0.000000 |
| 447IDD2P1=0.000000 | 447IDD2P1=0.032000 |
| 448IDD2P12=0.000000 | 448IDD2P12=0.000000 |
| 449IDD3N=0.057000 | 449IDD3N=0.038000 |
| 450IDD3N2=0.000000 451IDD3P0=0.000000 452IDD3P02=0.000000 | 450IDD3N2=0.000000 451IDD3P0=0.000000 452IDD3P02=0.000000 |
| 453IDD3P1=0.000000 | 453IDD3P1=0.038000 |
| 454IDD3P12=0.000000 | 454IDD3P12=0.000000 |
| 455IDD4R=0.187000 | 455IDD4R=0.157000 |
| 456IDD4R2=0.000000 | 456IDD4R2=0.000000 |
| 457IDD4W=0.165000 | 457IDD4W=0.125000 |
| 458IDD4W2=0.000000 | 458IDD4W2=0.000000 |
| 459IDD5=0.220000 | 459IDD5=0.235000 |
| 460IDD52=0.000000 | 460IDD52=0.000000 |
| 461IDD6=0.000000 | 461IDD6=0.020000 |
| 462IDD62=0.000000 463VDD=1.500000 464VDD2=0.000000 465activation_limit=4 466addr_mapping=RoRaBaCoCh 467bank_groups_per_rank=0 468banks_per_rank=8 469burst_length=8 470channels=1 471clk_domain=system.clk_domain 472conf_table_reported=true 473default_p_state=UNDEFINED 474device_bus_width=8 475device_rowbuffer_size=1024 476device_size=536870912 477devices_per_rank=8 478dll=true 479eventq_index=0 480in_addr_map=true | 462IDD62=0.000000 463VDD=1.500000 464VDD2=0.000000 465activation_limit=4 466addr_mapping=RoRaBaCoCh 467bank_groups_per_rank=0 468banks_per_rank=8 469burst_length=8 470channels=1 471clk_domain=system.clk_domain 472conf_table_reported=true 473default_p_state=UNDEFINED 474device_bus_width=8 475device_rowbuffer_size=1024 476device_size=536870912 477devices_per_rank=8 478dll=true 479eventq_index=0 480in_addr_map=true |
| 481kvm_map=true |
|
| 481max_accesses_per_row=16 482mem_sched_policy=frfcfs 483min_writes_per_switch=16 484null=false 485p_state_clk_gate_bins=20 486p_state_clk_gate_max=1000000000000 487p_state_clk_gate_min=1000 488page_policy=open_adaptive 489power_model=Null | 482max_accesses_per_row=16 483mem_sched_policy=frfcfs 484min_writes_per_switch=16 485null=false 486p_state_clk_gate_bins=20 487p_state_clk_gate_max=1000000000000 488p_state_clk_gate_min=1000 489page_policy=open_adaptive 490power_model=Null |
| 490range=0:536870911 | 491range=0:536870911:0:0:0:0 |
| 491ranks_per_channel=2 492read_buffer_size=32 493static_backend_latency=10000 494static_frontend_latency=10000 495tBURST=5000 496tCCD_L=0 497tCK=1250 498tCL=13750 --- 5 unchanged lines hidden (view full) --- 504tRP=13750 505tRRD=6000 506tRRD_L=0 507tRTP=7500 508tRTW=2500 509tWR=15000 510tWTR=7500 511tXAW=30000 | 492ranks_per_channel=2 493read_buffer_size=32 494static_backend_latency=10000 495static_frontend_latency=10000 496tBURST=5000 497tCCD_L=0 498tCK=1250 499tCL=13750 --- 5 unchanged lines hidden (view full) --- 505tRP=13750 506tRRD=6000 507tRRD_L=0 508tRTP=7500 509tRTW=2500 510tWR=15000 511tWTR=7500 512tXAW=30000 |
| 512tXP=0 | 513tXP=6000 |
| 513tXPDLL=0 | 514tXPDLL=0 |
| 514tXS=0 | 515tXS=270000 |
| 515tXSDLL=0 516write_buffer_size=64 517write_high_thresh_perc=85 518write_low_thresh_perc=50 519port=system.membus.master[0] 520 521[system.membus] 522type=CoherentXBar | 516tXSDLL=0 517write_buffer_size=64 518write_high_thresh_perc=85 519write_low_thresh_perc=50 520port=system.membus.master[0] 521 522[system.membus] 523type=CoherentXBar |
| 524children=snoop_filter |
|
| 523clk_domain=system.clk_domain 524default_p_state=UNDEFINED 525eventq_index=0 526forward_latency=4 527frontend_latency=3 528p_state_clk_gate_bins=20 529p_state_clk_gate_max=1000000000000 530p_state_clk_gate_min=1000 531point_of_coherency=true 532power_model=Null 533response_latency=2 | 525clk_domain=system.clk_domain 526default_p_state=UNDEFINED 527eventq_index=0 528forward_latency=4 529frontend_latency=3 530p_state_clk_gate_bins=20 531p_state_clk_gate_max=1000000000000 532p_state_clk_gate_min=1000 533point_of_coherency=true 534power_model=Null 535response_latency=2 |
| 534snoop_filter=Null | 536snoop_filter=system.membus.snoop_filter |
| 535snoop_response_latency=4 536system=system 537use_default_range=false 538width=16 539master=system.mem_ctrl.port 540slave=system.l2cache.mem_side system.system_port 541 | 537snoop_response_latency=4 538system=system 539use_default_range=false 540width=16 541master=system.mem_ctrl.port 542slave=system.l2cache.mem_side system.system_port 543 |
| 544[system.membus.snoop_filter] 545type=SnoopFilter 546eventq_index=0 547lookup_latency=1 548max_capacity=8388608 549system=system 550 |
|