Cross Reference: /gem5/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini

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config.ini (11680:b4d943429dc6)	config.ini (11960:c7bf1b698ccd)
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges=0:536870911:0:0:0:0 27memories=system.mem_ctrl 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[1] 47 48[system.clk_domain] 49type=SrcClockDomain 50children=voltage_domain 51clock=1000 52domain_id=-1 53eventq_index=0 54init_perf_level=0 55voltage_domain=system.clk_domain.voltage_domain 56 57[system.clk_domain.voltage_domain] 58type=VoltageDomain 59eventq_index=0 60voltage=1.000000 61 62[system.cpu] 63type=TimingSimpleCPU 64children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer workload 65branchPred=Null 66checker=Null 67clk_domain=system.clk_domain 68cpu_id=-1 69default_p_state=UNDEFINED 70do_checkpoint_insts=true 71do_quiesce=true 72do_statistics_insts=true 73dstage2_mmu=system.cpu.dstage2_mmu 74dtb=system.cpu.dtb 75eventq_index=0 76function_trace=false 77function_trace_start=0 78interrupts=system.cpu.interrupts 79isa=system.cpu.isa 80istage2_mmu=system.cpu.istage2_mmu 81itb=system.cpu.itb 82max_insts_all_threads=0 83max_insts_any_thread=0 84max_loads_all_threads=0 85max_loads_any_thread=0 86numThreads=1 87p_state_clk_gate_bins=20 88p_state_clk_gate_max=1000000000000 89p_state_clk_gate_min=1000 90power_model=Null 91profile=0 92progress_interval=0 93simpoint_start_insts= 94socket_id=0 95switched_out=false	1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17default_p_state=UNDEFINED 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges=0:536870911:0:0:0:0 27memories=system.mem_ctrl 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[1] 47 48[system.clk_domain] 49type=SrcClockDomain 50children=voltage_domain 51clock=1000 52domain_id=-1 53eventq_index=0 54init_perf_level=0 55voltage_domain=system.clk_domain.voltage_domain 56 57[system.clk_domain.voltage_domain] 58type=VoltageDomain 59eventq_index=0 60voltage=1.000000 61 62[system.cpu] 63type=TimingSimpleCPU 64children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer workload 65branchPred=Null 66checker=Null 67clk_domain=system.clk_domain 68cpu_id=-1 69default_p_state=UNDEFINED 70do_checkpoint_insts=true 71do_quiesce=true 72do_statistics_insts=true 73dstage2_mmu=system.cpu.dstage2_mmu 74dtb=system.cpu.dtb 75eventq_index=0 76function_trace=false 77function_trace_start=0 78interrupts=system.cpu.interrupts 79isa=system.cpu.isa 80istage2_mmu=system.cpu.istage2_mmu 81itb=system.cpu.itb 82max_insts_all_threads=0 83max_insts_any_thread=0 84max_loads_all_threads=0 85max_loads_any_thread=0 86numThreads=1 87p_state_clk_gate_bins=20 88p_state_clk_gate_max=1000000000000 89p_state_clk_gate_min=1000 90power_model=Null 91profile=0 92progress_interval=0 93simpoint_start_insts= 94socket_id=0 95switched_out=false
	96syscallRetryLatency=10000
96system=system 97tracer=system.cpu.tracer 98workload=system.cpu.workload 99dcache_port=system.cpu.dcache.cpu_side 100icache_port=system.cpu.icache.cpu_side 101 102[system.cpu.dcache] 103type=Cache 104children=tags 105addr_ranges=0:18446744073709551615:0:0:0:0 106assoc=2 107clk_domain=system.clk_domain 108clusivity=mostly_incl	97system=system 98tracer=system.cpu.tracer 99workload=system.cpu.workload 100dcache_port=system.cpu.dcache.cpu_side 101icache_port=system.cpu.icache.cpu_side 102 103[system.cpu.dcache] 104type=Cache 105children=tags 106addr_ranges=0:18446744073709551615:0:0:0:0 107assoc=2 108clk_domain=system.clk_domain 109clusivity=mostly_incl
	110data_latency=2
109default_p_state=UNDEFINED 110demand_mshr_reserve=1 111eventq_index=0	111default_p_state=UNDEFINED 112demand_mshr_reserve=1 113eventq_index=0
112hit_latency=2
113is_read_only=false 114max_miss_count=0 115mshrs=4 116p_state_clk_gate_bins=20 117p_state_clk_gate_max=1000000000000 118p_state_clk_gate_min=1000 119power_model=Null 120prefetch_on_access=false 121prefetcher=Null 122response_latency=2 123sequential_access=false 124size=65536 125system=system	114is_read_only=false 115max_miss_count=0 116mshrs=4 117p_state_clk_gate_bins=20 118p_state_clk_gate_max=1000000000000 119p_state_clk_gate_min=1000 120power_model=Null 121prefetch_on_access=false 122prefetcher=Null 123response_latency=2 124sequential_access=false 125size=65536 126system=system
	127tag_latency=2
126tags=system.cpu.dcache.tags 127tgts_per_mshr=20 128write_buffers=8 129writeback_clean=false 130cpu_side=system.cpu.dcache_port 131mem_side=system.l2bus.slave[1] 132 133[system.cpu.dcache.tags] 134type=LRU 135assoc=2 136block_size=64 137clk_domain=system.clk_domain	128tags=system.cpu.dcache.tags 129tgts_per_mshr=20 130write_buffers=8 131writeback_clean=false 132cpu_side=system.cpu.dcache_port 133mem_side=system.l2bus.slave[1] 134 135[system.cpu.dcache.tags] 136type=LRU 137assoc=2 138block_size=64 139clk_domain=system.clk_domain
	140data_latency=2
138default_p_state=UNDEFINED 139eventq_index=0	141default_p_state=UNDEFINED 142eventq_index=0
140hit_latency=2
141p_state_clk_gate_bins=20 142p_state_clk_gate_max=1000000000000 143p_state_clk_gate_min=1000 144power_model=Null 145sequential_access=false 146size=65536	143p_state_clk_gate_bins=20 144p_state_clk_gate_max=1000000000000 145p_state_clk_gate_min=1000 146power_model=Null 147sequential_access=false 148size=65536
	149tag_latency=2
147 148[system.cpu.dstage2_mmu] 149type=ArmStage2MMU 150children=stage2_tlb 151eventq_index=0 152stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 153sys=system 154tlb=system.cpu.dtb 155 156[system.cpu.dstage2_mmu.stage2_tlb] 157type=ArmTLB 158children=walker 159eventq_index=0 160is_stage2=true 161size=32 162walker=system.cpu.dstage2_mmu.stage2_tlb.walker 163 164[system.cpu.dstage2_mmu.stage2_tlb.walker] 165type=ArmTableWalker 166clk_domain=system.clk_domain 167default_p_state=UNDEFINED 168eventq_index=0 169is_stage2=true 170num_squash_per_cycle=2 171p_state_clk_gate_bins=20 172p_state_clk_gate_max=1000000000000 173p_state_clk_gate_min=1000 174power_model=Null 175sys=system 176 177[system.cpu.dtb] 178type=ArmTLB 179children=walker 180eventq_index=0 181is_stage2=false 182size=64 183walker=system.cpu.dtb.walker 184 185[system.cpu.dtb.walker] 186type=ArmTableWalker 187clk_domain=system.clk_domain 188default_p_state=UNDEFINED 189eventq_index=0 190is_stage2=false 191num_squash_per_cycle=2 192p_state_clk_gate_bins=20 193p_state_clk_gate_max=1000000000000 194p_state_clk_gate_min=1000 195power_model=Null 196sys=system 197 198[system.cpu.icache] 199type=Cache 200children=tags 201addr_ranges=0:18446744073709551615:0:0:0:0 202assoc=2 203clk_domain=system.clk_domain 204clusivity=mostly_incl	150 151[system.cpu.dstage2_mmu] 152type=ArmStage2MMU 153children=stage2_tlb 154eventq_index=0 155stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb 156sys=system 157tlb=system.cpu.dtb 158 159[system.cpu.dstage2_mmu.stage2_tlb] 160type=ArmTLB 161children=walker 162eventq_index=0 163is_stage2=true 164size=32 165walker=system.cpu.dstage2_mmu.stage2_tlb.walker 166 167[system.cpu.dstage2_mmu.stage2_tlb.walker] 168type=ArmTableWalker 169clk_domain=system.clk_domain 170default_p_state=UNDEFINED 171eventq_index=0 172is_stage2=true 173num_squash_per_cycle=2 174p_state_clk_gate_bins=20 175p_state_clk_gate_max=1000000000000 176p_state_clk_gate_min=1000 177power_model=Null 178sys=system 179 180[system.cpu.dtb] 181type=ArmTLB 182children=walker 183eventq_index=0 184is_stage2=false 185size=64 186walker=system.cpu.dtb.walker 187 188[system.cpu.dtb.walker] 189type=ArmTableWalker 190clk_domain=system.clk_domain 191default_p_state=UNDEFINED 192eventq_index=0 193is_stage2=false 194num_squash_per_cycle=2 195p_state_clk_gate_bins=20 196p_state_clk_gate_max=1000000000000 197p_state_clk_gate_min=1000 198power_model=Null 199sys=system 200 201[system.cpu.icache] 202type=Cache 203children=tags 204addr_ranges=0:18446744073709551615:0:0:0:0 205assoc=2 206clk_domain=system.clk_domain 207clusivity=mostly_incl
	208data_latency=2
205default_p_state=UNDEFINED 206demand_mshr_reserve=1 207eventq_index=0	209default_p_state=UNDEFINED 210demand_mshr_reserve=1 211eventq_index=0
208hit_latency=2
209is_read_only=false 210max_miss_count=0 211mshrs=4 212p_state_clk_gate_bins=20 213p_state_clk_gate_max=1000000000000 214p_state_clk_gate_min=1000 215power_model=Null 216prefetch_on_access=false 217prefetcher=Null 218response_latency=2 219sequential_access=false 220size=16384 221system=system	212is_read_only=false 213max_miss_count=0 214mshrs=4 215p_state_clk_gate_bins=20 216p_state_clk_gate_max=1000000000000 217p_state_clk_gate_min=1000 218power_model=Null 219prefetch_on_access=false 220prefetcher=Null 221response_latency=2 222sequential_access=false 223size=16384 224system=system
	225tag_latency=2
222tags=system.cpu.icache.tags 223tgts_per_mshr=20 224write_buffers=8 225writeback_clean=false 226cpu_side=system.cpu.icache_port 227mem_side=system.l2bus.slave[0] 228 229[system.cpu.icache.tags] 230type=LRU 231assoc=2 232block_size=64 233clk_domain=system.clk_domain	226tags=system.cpu.icache.tags 227tgts_per_mshr=20 228write_buffers=8 229writeback_clean=false 230cpu_side=system.cpu.icache_port 231mem_side=system.l2bus.slave[0] 232 233[system.cpu.icache.tags] 234type=LRU 235assoc=2 236block_size=64 237clk_domain=system.clk_domain
	238data_latency=2
234default_p_state=UNDEFINED 235eventq_index=0	239default_p_state=UNDEFINED 240eventq_index=0
236hit_latency=2
237p_state_clk_gate_bins=20 238p_state_clk_gate_max=1000000000000 239p_state_clk_gate_min=1000 240power_model=Null 241sequential_access=false 242size=16384	241p_state_clk_gate_bins=20 242p_state_clk_gate_max=1000000000000 243p_state_clk_gate_min=1000 244power_model=Null 245sequential_access=false 246size=16384
	247tag_latency=2
243 244[system.cpu.interrupts] 245type=ArmInterrupts 246eventq_index=0 247 248[system.cpu.isa] 249type=ArmISA 250decoderFlavour=Generic 251eventq_index=0 252fpsid=1090793632 253id_aa64afr0_el1=0 254id_aa64afr1_el1=0 255id_aa64dfr0_el1=1052678 256id_aa64dfr1_el1=0 257id_aa64isar0_el1=0 258id_aa64isar1_el1=0 259id_aa64mmfr0_el1=15728642 260id_aa64mmfr1_el1=0	248 249[system.cpu.interrupts] 250type=ArmInterrupts 251eventq_index=0 252 253[system.cpu.isa] 254type=ArmISA 255decoderFlavour=Generic 256eventq_index=0 257fpsid=1090793632 258id_aa64afr0_el1=0 259id_aa64afr1_el1=0 260id_aa64dfr0_el1=1052678 261id_aa64dfr1_el1=0 262id_aa64isar0_el1=0 263id_aa64isar1_el1=0 264id_aa64mmfr0_el1=15728642 265id_aa64mmfr1_el1=0
261id_aa64pfr0_el1=34 262id_aa64pfr1_el1=0
263id_isar0=34607377 264id_isar1=34677009 265id_isar2=555950401 266id_isar3=17899825 267id_isar4=268501314 268id_isar5=0 269id_mmfr0=270536963 270id_mmfr1=0 271id_mmfr2=19070976 272id_mmfr3=34611729	266id_isar0=34607377 267id_isar1=34677009 268id_isar2=555950401 269id_isar3=17899825 270id_isar4=268501314 271id_isar5=0 272id_mmfr0=270536963 273id_mmfr1=0 274id_mmfr2=19070976 275id_mmfr3=34611729
273id_pfr0=49 274id_pfr1=4113
275midr=1091551472 276pmu=Null 277system=system 278 279[system.cpu.istage2_mmu] 280type=ArmStage2MMU 281children=stage2_tlb 282eventq_index=0 283stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 284sys=system 285tlb=system.cpu.itb 286 287[system.cpu.istage2_mmu.stage2_tlb] 288type=ArmTLB 289children=walker 290eventq_index=0 291is_stage2=true 292size=32 293walker=system.cpu.istage2_mmu.stage2_tlb.walker 294 295[system.cpu.istage2_mmu.stage2_tlb.walker] 296type=ArmTableWalker 297clk_domain=system.clk_domain 298default_p_state=UNDEFINED 299eventq_index=0 300is_stage2=true 301num_squash_per_cycle=2 302p_state_clk_gate_bins=20 303p_state_clk_gate_max=1000000000000 304p_state_clk_gate_min=1000 305power_model=Null 306sys=system 307 308[system.cpu.itb] 309type=ArmTLB 310children=walker 311eventq_index=0 312is_stage2=false 313size=64 314walker=system.cpu.itb.walker 315 316[system.cpu.itb.walker] 317type=ArmTableWalker 318clk_domain=system.clk_domain 319default_p_state=UNDEFINED 320eventq_index=0 321is_stage2=false 322num_squash_per_cycle=2 323p_state_clk_gate_bins=20 324p_state_clk_gate_max=1000000000000 325p_state_clk_gate_min=1000 326power_model=Null 327sys=system 328 329[system.cpu.tracer] 330type=ExeTracer 331eventq_index=0 332 333[system.cpu.workload]	276midr=1091551472 277pmu=Null 278system=system 279 280[system.cpu.istage2_mmu] 281type=ArmStage2MMU 282children=stage2_tlb 283eventq_index=0 284stage2_tlb=system.cpu.istage2_mmu.stage2_tlb 285sys=system 286tlb=system.cpu.itb 287 288[system.cpu.istage2_mmu.stage2_tlb] 289type=ArmTLB 290children=walker 291eventq_index=0 292is_stage2=true 293size=32 294walker=system.cpu.istage2_mmu.stage2_tlb.walker 295 296[system.cpu.istage2_mmu.stage2_tlb.walker] 297type=ArmTableWalker 298clk_domain=system.clk_domain 299default_p_state=UNDEFINED 300eventq_index=0 301is_stage2=true 302num_squash_per_cycle=2 303p_state_clk_gate_bins=20 304p_state_clk_gate_max=1000000000000 305p_state_clk_gate_min=1000 306power_model=Null 307sys=system 308 309[system.cpu.itb] 310type=ArmTLB 311children=walker 312eventq_index=0 313is_stage2=false 314size=64 315walker=system.cpu.itb.walker 316 317[system.cpu.itb.walker] 318type=ArmTableWalker 319clk_domain=system.clk_domain 320default_p_state=UNDEFINED 321eventq_index=0 322is_stage2=false 323num_squash_per_cycle=2 324p_state_clk_gate_bins=20 325p_state_clk_gate_max=1000000000000 326p_state_clk_gate_min=1000 327power_model=Null 328sys=system 329 330[system.cpu.tracer] 331type=ExeTracer 332eventq_index=0 333 334[system.cpu.workload]
334type=LiveProcess	335type=Process
335cmd=tests/test-progs/hello/bin/arm/linux/hello 336cwd= 337drivers= 338egid=100 339env= 340errout=cerr 341euid=100 342eventq_index=0 343executable= 344gid=100 345input=cin 346kvmInSE=false	336cmd=tests/test-progs/hello/bin/arm/linux/hello 337cwd= 338drivers= 339egid=100 340env= 341errout=cerr 342euid=100 343eventq_index=0 344executable= 345gid=100 346input=cin 347kvmInSE=false
347max_stack_size=67108864	348maxStackSize=67108864
348output=cout	349output=cout
	350pgid=100
349pid=100	351pid=100
350ppid=99	352ppid=0
351simpoint=0 352system=system 353uid=100 354useArchPT=false 355 356[system.dvfs_handler] 357type=DVFSHandler 358domains= 359enable=false 360eventq_index=0 361sys_clk_domain=system.clk_domain 362transition_latency=100000000 363 364[system.l2bus] 365type=CoherentXBar 366children=snoop_filter 367clk_domain=system.clk_domain 368default_p_state=UNDEFINED 369eventq_index=0 370forward_latency=0 371frontend_latency=1 372p_state_clk_gate_bins=20 373p_state_clk_gate_max=1000000000000 374p_state_clk_gate_min=1000 375point_of_coherency=false 376power_model=Null 377response_latency=1 378snoop_filter=system.l2bus.snoop_filter 379snoop_response_latency=1 380system=system 381use_default_range=false 382width=32 383master=system.l2cache.cpu_side 384slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 385 386[system.l2bus.snoop_filter] 387type=SnoopFilter 388eventq_index=0 389lookup_latency=0 390max_capacity=8388608 391system=system 392 393[system.l2cache] 394type=Cache 395children=tags 396addr_ranges=0:18446744073709551615:0:0:0:0 397assoc=8 398clk_domain=system.clk_domain 399clusivity=mostly_incl	353simpoint=0 354system=system 355uid=100 356useArchPT=false 357 358[system.dvfs_handler] 359type=DVFSHandler 360domains= 361enable=false 362eventq_index=0 363sys_clk_domain=system.clk_domain 364transition_latency=100000000 365 366[system.l2bus] 367type=CoherentXBar 368children=snoop_filter 369clk_domain=system.clk_domain 370default_p_state=UNDEFINED 371eventq_index=0 372forward_latency=0 373frontend_latency=1 374p_state_clk_gate_bins=20 375p_state_clk_gate_max=1000000000000 376p_state_clk_gate_min=1000 377point_of_coherency=false 378power_model=Null 379response_latency=1 380snoop_filter=system.l2bus.snoop_filter 381snoop_response_latency=1 382system=system 383use_default_range=false 384width=32 385master=system.l2cache.cpu_side 386slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 387 388[system.l2bus.snoop_filter] 389type=SnoopFilter 390eventq_index=0 391lookup_latency=0 392max_capacity=8388608 393system=system 394 395[system.l2cache] 396type=Cache 397children=tags 398addr_ranges=0:18446744073709551615:0:0:0:0 399assoc=8 400clk_domain=system.clk_domain 401clusivity=mostly_incl
	402data_latency=20
400default_p_state=UNDEFINED 401demand_mshr_reserve=1 402eventq_index=0	403default_p_state=UNDEFINED 404demand_mshr_reserve=1 405eventq_index=0
403hit_latency=20
404is_read_only=false 405max_miss_count=0 406mshrs=20 407p_state_clk_gate_bins=20 408p_state_clk_gate_max=1000000000000 409p_state_clk_gate_min=1000 410power_model=Null 411prefetch_on_access=false 412prefetcher=Null 413response_latency=20 414sequential_access=false 415size=262144 416system=system	406is_read_only=false 407max_miss_count=0 408mshrs=20 409p_state_clk_gate_bins=20 410p_state_clk_gate_max=1000000000000 411p_state_clk_gate_min=1000 412power_model=Null 413prefetch_on_access=false 414prefetcher=Null 415response_latency=20 416sequential_access=false 417size=262144 418system=system
	419tag_latency=20
417tags=system.l2cache.tags 418tgts_per_mshr=12 419write_buffers=8 420writeback_clean=false 421cpu_side=system.l2bus.master[0] 422mem_side=system.membus.slave[0] 423 424[system.l2cache.tags] 425type=LRU 426assoc=8 427block_size=64 428clk_domain=system.clk_domain	420tags=system.l2cache.tags 421tgts_per_mshr=12 422write_buffers=8 423writeback_clean=false 424cpu_side=system.l2bus.master[0] 425mem_side=system.membus.slave[0] 426 427[system.l2cache.tags] 428type=LRU 429assoc=8 430block_size=64 431clk_domain=system.clk_domain
	432data_latency=20
429default_p_state=UNDEFINED 430eventq_index=0	433default_p_state=UNDEFINED 434eventq_index=0
431hit_latency=20
432p_state_clk_gate_bins=20 433p_state_clk_gate_max=1000000000000 434p_state_clk_gate_min=1000 435power_model=Null 436sequential_access=false 437size=262144	435p_state_clk_gate_bins=20 436p_state_clk_gate_max=1000000000000 437p_state_clk_gate_min=1000 438power_model=Null 439sequential_access=false 440size=262144
	441tag_latency=20
438 439[system.mem_ctrl] 440type=DRAMCtrl 441IDD0=0.055000 442IDD02=0.000000 443IDD2N=0.032000 444IDD2N2=0.000000 445IDD2P0=0.000000 446IDD2P02=0.000000 447IDD2P1=0.032000 448IDD2P12=0.000000 449IDD3N=0.038000 450IDD3N2=0.000000 451IDD3P0=0.000000 452IDD3P02=0.000000 453IDD3P1=0.038000 454IDD3P12=0.000000 455IDD4R=0.157000 456IDD4R2=0.000000 457IDD4W=0.125000 458IDD4W2=0.000000 459IDD5=0.235000 460IDD52=0.000000 461IDD6=0.020000 462IDD62=0.000000 463VDD=1.500000 464VDD2=0.000000 465activation_limit=4 466addr_mapping=RoRaBaCoCh 467bank_groups_per_rank=0 468banks_per_rank=8 469burst_length=8 470channels=1 471clk_domain=system.clk_domain 472conf_table_reported=true 473default_p_state=UNDEFINED 474device_bus_width=8 475device_rowbuffer_size=1024 476device_size=536870912 477devices_per_rank=8 478dll=true 479eventq_index=0 480in_addr_map=true 481kvm_map=true 482max_accesses_per_row=16 483mem_sched_policy=frfcfs 484min_writes_per_switch=16 485null=false 486p_state_clk_gate_bins=20 487p_state_clk_gate_max=1000000000000 488p_state_clk_gate_min=1000 489page_policy=open_adaptive 490power_model=Null 491range=0:536870911:0:0:0:0 492ranks_per_channel=2 493read_buffer_size=32 494static_backend_latency=10000 495static_frontend_latency=10000 496tBURST=5000 497tCCD_L=0 498tCK=1250 499tCL=13750 500tCS=2500 501tRAS=35000 502tRCD=13750 503tREFI=7800000 504tRFC=260000 505tRP=13750 506tRRD=6000 507tRRD_L=0 508tRTP=7500 509tRTW=2500 510tWR=15000 511tWTR=7500 512tXAW=30000 513tXP=6000 514tXPDLL=0 515tXS=270000 516tXSDLL=0 517write_buffer_size=64 518write_high_thresh_perc=85 519write_low_thresh_perc=50 520port=system.membus.master[0] 521 522[system.membus] 523type=CoherentXBar 524children=snoop_filter 525clk_domain=system.clk_domain 526default_p_state=UNDEFINED 527eventq_index=0 528forward_latency=4 529frontend_latency=3 530p_state_clk_gate_bins=20 531p_state_clk_gate_max=1000000000000 532p_state_clk_gate_min=1000 533point_of_coherency=true 534power_model=Null 535response_latency=2 536snoop_filter=system.membus.snoop_filter 537snoop_response_latency=4 538system=system 539use_default_range=false 540width=16 541master=system.mem_ctrl.port 542slave=system.l2cache.mem_side system.system_port 543 544[system.membus.snoop_filter] 545type=SnoopFilter 546eventq_index=0 547lookup_latency=1 548max_capacity=8388608 549system=system 550	442 443[system.mem_ctrl] 444type=DRAMCtrl 445IDD0=0.055000 446IDD02=0.000000 447IDD2N=0.032000 448IDD2N2=0.000000 449IDD2P0=0.000000 450IDD2P02=0.000000 451IDD2P1=0.032000 452IDD2P12=0.000000 453IDD3N=0.038000 454IDD3N2=0.000000 455IDD3P0=0.000000 456IDD3P02=0.000000 457IDD3P1=0.038000 458IDD3P12=0.000000 459IDD4R=0.157000 460IDD4R2=0.000000 461IDD4W=0.125000 462IDD4W2=0.000000 463IDD5=0.235000 464IDD52=0.000000 465IDD6=0.020000 466IDD62=0.000000 467VDD=1.500000 468VDD2=0.000000 469activation_limit=4 470addr_mapping=RoRaBaCoCh 471bank_groups_per_rank=0 472banks_per_rank=8 473burst_length=8 474channels=1 475clk_domain=system.clk_domain 476conf_table_reported=true 477default_p_state=UNDEFINED 478device_bus_width=8 479device_rowbuffer_size=1024 480device_size=536870912 481devices_per_rank=8 482dll=true 483eventq_index=0 484in_addr_map=true 485kvm_map=true 486max_accesses_per_row=16 487mem_sched_policy=frfcfs 488min_writes_per_switch=16 489null=false 490p_state_clk_gate_bins=20 491p_state_clk_gate_max=1000000000000 492p_state_clk_gate_min=1000 493page_policy=open_adaptive 494power_model=Null 495range=0:536870911:0:0:0:0 496ranks_per_channel=2 497read_buffer_size=32 498static_backend_latency=10000 499static_frontend_latency=10000 500tBURST=5000 501tCCD_L=0 502tCK=1250 503tCL=13750 504tCS=2500 505tRAS=35000 506tRCD=13750 507tREFI=7800000 508tRFC=260000 509tRP=13750 510tRRD=6000 511tRRD_L=0 512tRTP=7500 513tRTW=2500 514tWR=15000 515tWTR=7500 516tXAW=30000 517tXP=6000 518tXPDLL=0 519tXS=270000 520tXSDLL=0 521write_buffer_size=64 522write_high_thresh_perc=85 523write_low_thresh_perc=50 524port=system.membus.master[0] 525 526[system.membus] 527type=CoherentXBar 528children=snoop_filter 529clk_domain=system.clk_domain 530default_p_state=UNDEFINED 531eventq_index=0 532forward_latency=4 533frontend_latency=3 534p_state_clk_gate_bins=20 535p_state_clk_gate_max=1000000000000 536p_state_clk_gate_min=1000 537point_of_coherency=true 538power_model=Null 539response_latency=2 540snoop_filter=system.membus.snoop_filter 541snoop_response_latency=4 542system=system 543use_default_range=false 544width=16 545master=system.mem_ctrl.port 546slave=system.l2cache.mem_side system.system_port 547 548[system.membus.snoop_filter] 549type=SnoopFilter 550eventq_index=0 551lookup_latency=1 552max_capacity=8388608 553system=system 554